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IMX8MPCEC データシート(PDF) 73 Page - NXP Semiconductors |
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IMX8MPCEC データシート(HTML) 73 Page - NXP Semiconductors |
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73 / 111 page  Electrical characteristics i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 NXP Semiconductors 73 3.8.12 FlexSPI timing parameters Measurement is with a load of 35 pF on SCK and SIO pins and an input slew rate of 1 V/ns. 3.8.12.1 FlexSPI input/read timing There are three sources for the internal sample clock for FlexSPI read data: • Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0) • Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1) • Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) The following sections describe input signal timing for each of these four internal sample clock sources. 3.8.12.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2 Table 55. PWM output timing parameters ID Parameter Min Max Unit PWM Module Clock Frequency 0 66 (ipg_clk) MHz P1 PWM output pulse width high 12 — ns P2 PWM output pulse width low 12 — ns Table 56. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0 Symbol Parameter Min. Max. Unit Notes — [D:] Frequency of operation — 66 MHz — F1 [D:] Setup time for incoming data 8.67 — ns 1 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. F2 [D:] Hold time for incoming data 0 — ns — Table 57. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2 Symbol Parameter Min. Max. Unit Notes — [D:] Frequency of operation — 133 MHz — F1 [D:] Setup time for incoming data 1.5 — ns 1 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. F2 [D:] Hold time for incoming data 1 — ns — |
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