IMX8MPCEC datasheet(13/111 Pages) NXP

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Modules list

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

SDMA

Smart Direct Memory Access

The SDMA is a multichannel flexible DMA engine. It helps in

maximizing system performance by offloading the various cores in

dynamic data routing. It has the following features:

• Powered by a 16-bit Instruction-Set micro-RISC engine

• Multi channel DMA supporting up to 32 time-division multiplexed

DMA channels

• 48 events with total flexibility to trigger any combination of

channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between Arm and SDMA

• Very fast Context-Switching with 2-level priority based preemptive

multi tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment,

decrement, and no address changes on source and destination

address)

• DMA ports can handle unidirectional and bidirectional flows (Copy

mode)

• Up to 8-word buffer for configurable burst transfers for EMIv2.5

• Support of byte-swapping and CRC calculations

• Library of Scripts and API is available

SJC

Secure JTAG Controller

The SJC provides JTAG interface (designed to be compatible with

JTAG TAP standards) to internal logic. The i.MX 8M Plus family of

processors uses JTAG port for production, testing, and system

debugging. Additionally, the SJC provides BSR (Boundary Scan

1149.1 and IEEE 1149.6 standards.

The JTAG port must be accessible during platform initial laboratory

bring-up, for manufacturing tests and troubleshooting, as well as for

software debugging by authorized entities. The i.MX 8M Plus SJC

incorporates three security modes for protecting against

unauthorized accesses. Modes are selected through eFUSE

configuration.

SNVS

Secure Non-Volatile Storage

Secure Non-Volatile Storage, including Secure Real Time Clock,

Security State Machine, Master Key Control, and Violation Detection

and reporting.

SPDIF1

Sony Philips Digital

Interconnect Format

A standard audio file transfer format, developed jointly by the Sony

and Phillips corporations. It supports Transmitter and Receiver

functionality.

System Bus (NoC)

Network-on-Chip

The module is used as central inter-connect fabric, which runs at

approximately 1/4 of the DRAM data rate, and links the bus master

to DRAM controller for high-throughput DRAM access.

Multiple additional NoCs as the high-performance inter-connect bus

fabric for high-speed initiators.

TEMPSENSOR

Temperature Sensor

Temperature sensor

TZASC

Trust-Zone Address Space

Controller

The TZASC (TZC-380 by Arm) provides security address region

control functions required for intended application. It is used on the

path to the DRAM controller.

Table 4. i.MX 8M Plus modules list (continued)

Block mnemonic

Block name

Brief description

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