VNF1048F datasheet(17/52 Pages) STMICROELECTRONICS

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Self Test

The following sections describe how the device supports the execution of the in-application tests, needed to

verify the proper behavior of the hardware diagnostic verification during product lifetime. Configuration, control

and check for each of the tests are performed in close relationship with micro-controller, through SPI interface

communication.

Activities related to self-test are possible in a specific device state (Self Test) in order to distinguish it from

operating modes (Stand-by, WakeUp, Unlocked and Locked modes), allowing to manage differently diagnostic

faults according to the hardware feature under test.

Self test control interface

The initialization of the Self Test sequence (selection of the Self Test, start and stop command) is done through

the Control Register 1 (CR#1). Results are accessible through the Status Register 5 (SR#5), Status Register 6

(SR#6) and Status Register 7 (SR#7).

4.1

Current Sense Self Test

The goal of the Current Sense Self Test is to verify the proper behavior of the full current-sense chain, from the

analog input to the digital output.

Starting from the Unlocked State, the Current sense Self Test is activated through a dedicated SPI frame. The

duration of this test is around 10 µs; the first 5 µs are intended to convert the value of the voltage across the

Rsense.

Once the Self Test is started, an internal current generator provides a current sink able to produce an additional

voltage drop of 100 mV at the input pin of the internal comparator.

The result of the Self Test is the difference between this converted value and the value already stored in SR#8

(HSHT), corresponding to the normal measurement performed during operation; such result is stored in SR#7

together with the Self Test status.

The transition from Self Test state to Unlocked state is automatically guaranteed after the test is completed

(around 10 µs) or if the test is stopped through S_T_STOP = 1 (Self Test aborted).

The transition from the Self Test state to the Locked state can occur in case of watchdog timeout or HWLO = 1

(Self Test aborted).

VNF1048F

Self Test

DS13084 - Rev 6

page 17/52

VNF1048F データシート(PDF) 17 Page - STMicroelectronics