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VNF1048F データシート(PDF) 27 Page - STMicroelectronics

部品番号 VNF1048F
部品情報  High-side switch Controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications
PDF  52 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNF1048F データシート(HTML) 27 Page - STMicroelectronics

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Table 26. Output data byte 2
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Table 27. Output data byte 3
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
6.4
Operating code definition
The SPI interface features four different addressing modes which are listed in Table 28.
Table 28. Operating codes
OC1
OC0
Meaning
0
0
Write operation
0
1
Read operation
1
0
Read and clear status operation
1
1
Read device information
6.5
Write mode
The write mode of the device allows to write the content of the input data byte into the addressed register (see list
of registers in Table 33. RAM memory map (ID 12.1)). Incoming data are sampled on the rising edge of the serial
clock (SCK), MSB first.
During the same sequence outgoing data are shifted out MSB first on the falling edge of the CSN pin and
subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte,
second, third and forth bytes to the previous content of the addressed register. Unused bits will be always read as
0.
Figure 10. SPI write operation
0
0
SDI
SDO
CSN
MSB
Address
Command Byte
(8 bits)
Global Status Byte
MSB
LSB
LSB
MSB
MSB
(previous content of register)
Data
(24 bits)
Data
LSB
LSB
GADG1010171330PS
VNF1048F
Operating code definition
DS13084 - Rev 6
page 27/52



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