VNF1048F datasheet(20/52 Pages) STMICROELECTRONICS

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4.3

External FET Stuck-on Self Test

The goal of this Self Test is to verify proper turn-off of the external power switch, by monitoring its VDS behavior in

time.

Starting from the Unlocked State, the external FET Stuck-on Self Test is activated through a dedicated SPI frame

(CR#1, S_T_START & S_T_CFG fields).

At execution start the external FET is automatically turned-off, regardless of its status during previous operations,

then continuous AtoD conversions of VDS voltage, sensed across external power switch terminals, are performed

in order to allow the user to monitor VDS evolution in time.

Data conversion values are made available through dedicated register SR#6 (S_T_STUCK field); in addition, a

specific bit informs the user if the data have been updated with a new measure or are still relative to the previous

one (UPDT_S_T_STUCK bit). Status of Self Test execution is available in the same register.

Self Test completion can be controlled directly by sending S_T_STOP command (CR#1, bit 8) or by setting

programmable VDS threshold (CR#2, VDS_THR field): in this case, Self Test is stopped automatically as soon

as the external FET VDS overcomes the aforementioned threshold and a specific bit is set to flag this situation

(SR#6, S_T_VDS_MAX2 bit). In both cases device FSM performs transition from Self Test to Unlocked state.

To be noted that diagnostic fault for normal operation (VDS_MAX, SR#1) is inhibited during execution, while all

the others are kept enabled; bypass switch control is left to the user.

The transition from the Self Test state to the Locked state can occur in case of watchdog timeout or HWLO = 1

(Self Test aborted).

VNF1048F

External FET Stuck-on Self Test

DS13084 - Rev 6

page 20/52

VNF1048F データシート(PDF) 20 Page - STMicroelectronics