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UPD17708 データシート(PDF) 20 Page - Renesas Technology Corp |
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UPD17708 データシート(HTML) 20 Page - Renesas Technology Corp |
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20 / 358 page  µPD17704, 17705, 17707, 17708, 17709 18 (5) P1A (P1A1) (input) Note This is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (6) P1C (P1C3/AD5, P1C2/AD4) (input) Note This is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (7) P1C (P1C1/AMIFC, P1C0/FMIFC) (input) Note This is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. VDD A/D converter CKSTOPNote VDD CKSTOPNote VDD VDD VDD General-purpose port High-ON resistance Frequency counter CKSTOPNote |
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