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M69KB128AA データシート(PDF) 14 Page - STMicroelectronics |
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M69KB128AA データシート(HTML) 14 Page - STMicroelectronics |
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14 / 68 page  4 Low-power modes M69KB128AA 14/68 4.3 Partial Array Self Refresh The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array. This mechanism enables the device to reduce the Standby current by refreshing only the part of the memory array that contains essential data. Different refresh options can be defined by setting the RCR0 to RCR2 bits of the RCR: ● Full array ● One eighth of the array ● One half of the array ● One quarter of the array ● None of the array. These memory areas can be located either at the top or bottom of the memory array. The WAIT signal is used for arbitration when a read/write operation is launched while an on- chip refresh is in progress. If locations are addressed while they are undergoing refresh, the WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see Figure 6: Refresh Collision during Synchronous Read Operation in Variable Latency mode). When the refresh operation is completed, the read or write operation will be allowed to continue normally. |
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