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M69KB128AA データシート(PDF) 24 Page - STMicroelectronics |
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M69KB128AA データシート(HTML) 24 Page - STMicroelectronics |
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24 / 68 page ![]() 6 Synchronous operating modes M69KB128AA 24/68 Table 7. Full Synchronous mode Synchronous Mode(1) 1. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated paragraph of the Section 6: Synchronous operating modes. Power K E L W G LB, UB WAIT CR A19 A18 A0- A22(2) 2. Except A18 and A19. DQ15- DQ0 Initial Burst Read Active (ICC) = VIL VIL VIH X VIL Low-Z VIL Valid Valid Valid X Subsequent Burst Read = VIL VIH X VIL VIL (3) 3. The above table shows the device behavior if both LB and UB are asserted, VIL. If either LB or UB is High, VIH, only one Byte will be input or output, according to the status of W. VIL XX Output Valid Initial Burst Write = VIL VIL VIL VIH X VIL Valid Valid Valid Input Valid Subsequent Burst Write = VIL VIH X VIH VIL (2) XX X X Input Valid Program Configuration Register (CR Controlled) = VIL VIL VIL VIH X VIH 00(RCR) 10(BCR) RCR/ BCR Data X Read Configuration Register (CR Controlled Method) = VIL VIL VIH VIL VIL VIH 00(RCR) 10(BCR) X1(DIDR) X RCR/ BCR/ DIDR Content No Operation Active (ICC) VIL VIL XX X X VIL XX Standby Standby (IPASR) VIL VIH XX X X High-Z VIL XHigh-Z Deep Power-Down Deep Power- Down (ICCPD) VIL VIH XX X X X X High-Z |
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