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MCP3919B データシート(PDF) 22 Page - Microchip Technology |
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MCP3919B データシート(HTML) 22 Page - Microchip Technology |
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22 / 81 page  MCP3919B DS20006995A-page 22 2025 Microchip Technology Inc. and its subsidiaries 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: • MCLK – Master Clock • AMCLK – Analog Master Clock • DMCLK – Digital Master Clock • DRCLK – Data Rate Clock • OSR – Oversampling Ratio • Offset Error • Gain Error • Integral Nonlinearity Error • Signal-to-Noise Ratio (SNR) • Signal-to-Noise Ratio and Distortion (SINAD) • Total Harmonic Distortion (THD) • Spurious-Free Dynamic Range (SFDR) • MCP3919B Delta-Sigma Architecture • Idle Tones • Dithering • Crosstalk • PSRR • CMRR • ADC Reset Mode • Hard Reset Mode (RESET = 0) • ADC Shutdown Mode • Full Shutdown Mode • Measurement Error 4.1 MCLK – Master Clock This is the fastest clock present on the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1. See Figure 4-1. 4.2 AMCLK – Analog Master Clock AMCLK is the clock frequency that is present on the analog portion of the device after prescaling has occurred via the PRE[1:0] bits (CONFIG0 register); see Equation 4-1. The analog portion includes the PGAs and the Delta-Sigma modulators. EQUATION 4-1: FIGURE 4-1: Clock Sub-Circuitry. 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device after prescaling and division by four (Equation 4-2). This is also the sampling frequency, which is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Figure 4-1. EQUATION 4-2: 4.4 DRCLK – Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). Each new data are signaled by a data ready pulse on the DR pin. This data rate is dependent on the OSR and the prescaler with the formula in Equation 4-3. EQUATION 4-3: TABLE 4-1: MCP3919B OVERSAMPLING RATIO SETTINGS CONFIG0 Analog Master Clock Prescale PRE[1:0] 00 AMCLK = MCLK/1 (default) 01 AMCLK = MCLK/2 10 AMCLK = MCLK/4 11 AMCLK = MCLK/8 AMCLK MCLK PRESCALE ------------------------------- = Xtal Oscillator MCLK OSC1 OSC2 Multiplexer OUT 0 1 1/4 1/OSR AMCLK DMCLK DRCLK Clock Divider Clock Divider Clock Divider OSR[2:0] PRE[1:0] CLKEXT Multiplexer OUT 0 1 MODE SCK DMCLK AMCLK 4 --------------------- MCLK 4 PRESCALE ---------------------------------------- == DRCLK DMCLK OSR ---------------------- AMCLK 4OSR --------------------- MCLK 4 OSR PRESCALE ----------------------------------------------------------- == = |
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