MCP3919B datasheet(49/81 Pages) MICROCHIP

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DS20006995A-page 49

MCP3919B

7.0

TWO-WIRE SERIAL

INTERFACE DESCRIPTION

7.1

OVERVIEW

The Two-Wire Interface mode is designed for applications

that require galvanic isolation. It allows a minimum

number of digital isolator channels, specifically one

bidirectional or two unidirectional channels to be

connected to the MCP3919B when interfacing through an

isolation barrier. This functionality reduces the total

system cost in an isolated applications system like a

polyphase shunt-based energy meter. It is recommended

to use the MCP3919B with the Two-Wire mode for digi-

tally isolated applications and with the SPI mode for other

applications where galvanic isolation is not required.

The principle of this Two-Wire Interface mode is simple:

it has a Serial Clock Input (SCK/MCLK) pin and a Serial

Data Output (SDO) pin, and it automatically sends

output data in packets (frames) at a DRCLK data rate

(every time new data are available on the ADC out-

puts). It has no serial input pin to diminish the number

of isolated channels. At the same time, the Serial Clock

(SCK) pin also becomes the Master Clock (MCLK)

input pin of the device and the part becomes fully

synchronous with SCK = MCLK. The system then

becomes fully synchronous and can be driven by only

one master clock for multiple phases, which ensures

proper synchronization and constant phase angle

between phases, which is important for an energy

metering application.

The SDO pin becomes the only output of the device

and is fully synchronous with the serial/master clock.

The SDO pin is never in high-impedance in this mode

and is, by default, at logic low when not transmitting

data. The SDO pin Idles logic low in this mode because

most of the digital isolator devices consume less

current in a logic low state than in a logic high state.

This effectively reduces the total power consumption of

a system with digital isolation devices.

When the part has entered Two-Wire mode, the logic

pins, RESET, SDI, CS, OSC1 and DR, become logic

input pins for the configuration of the device (respec-

tively, OSR0/OSR1/BOOST/GAIN0/GAIN1). These pins

need to have well-defined logic states for low-power

applications. These pins define the only settings that can

be modified in Two-Wire mode.

The MDAT0/1 pins are always disabled and kept in a

high-impedance state during the Two-Wire Interface

mode. These pins can be grounded for applications

exclusively using the Two-Wire Interface mode so that

the EMI/EMC susceptibility of the part is improved.

FIGURE 7-1:

MCP3919B Two-Wire Interface Typical Application Schematic.

7.2

Two-Wire Mode Configuration

Settings

When the user wants to exclusively use the Two-Wire

Interface mode in digitally isolated applications, the

OSC2 pin should always be in a logic high state, start-

ing from the power-up of the part. Otherwise, the user

can change the interface mode by toggling the OSC2/

MODE pin within a POR, a Hard Reset or a Watchdog

Timer Reset; the MODE pin is latched when exiting one

of these three types of Reset. When the part has

entered Two-Wire mode, the entire part configuration

keeps

its

default

settings

(see

Section 9.0

“MCP3919B Internal Registers” for the default set-

tings of all internal registers), except for the configura-

tion of the GAIN in Channel 0, the OSR and the BOOST

settings.

In Two-Wire Interface mode, the input pins, OSR0/OSR1/

BOOST/GAIN0/GAIN1, are latched on the OSC2/MODE

rising edge and should typically be directly connected

to DVDD or DGND, depending on the desired configura-

tion. These pins define the only configurable settings in

Two-Wire mode. If more settings are required by the

SDO

GAIN1

SCK/MCLK

OSR0

BOOST

CH0+

CH0-

CH1+

CH1-

MCP3919B

ANALOG

DIGITAL

SINC

PGA

GAIN=1x

SINC

PGA

Modulator

MOD<3:0>

MOD<7:4>

Modulator

Isolator

2-wire

Interface

OSR1

To SPI Ports

Of an MCU

GAIN0

MDAT0

MDAT1

Logic inputs

connected

to DVDD or

DGND

Main MCU/

CPU Board

Isolation

Barrier

Optional

connections to 2

additional isolators

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