MCP3919B datasheet(64/81 Pages) MICROCHIP

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MCP3919B

DS20006995A-page 64

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9.6

CONFIG0 Register –

Configuration Register 0

Name

Bits

Address

Cof.

CONFIG0

0x0D

R/W

CONFIG0 REGISTER

R/W-0

R/W-1

R/W-0

EN_OFFCAL EN_GAINCAL

DITHER[1:0]

BOOST[1:0]

PRE[1:0]

bit 23

bit 16

R/W-0

R/W-1

U-0

OSR[2:0]

—

bit 15

bit 8

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

VREFCAL[7:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23

EN_OFFCAL: 24-Bit Digital Offset Error Calibration on All Channels Enable bit

1 = Enabled; this mode does not add any group delay to the ADC data

0 = Disabled (default)

bit 22

EN_GAINCAL: 24-Bit Digital Gain Error Calibration on All Channels Enable/Disable bit

1 = Enabled; this mode adds a group delay on all channels of 24 DMCLK periods, all data ready pulses

are delayed by 24 DMCLK clock periods compared to the mode with EN_GAINCAL = 0

0 = Disabled (default)

bit 21-20

DITHER[1:0]: Dithering Circuit for Idle Tones Cancellation and Improved THD on All Channels Control bits

11 = Dithering on, Strength = Maximum (default)

10 = Dithering on, Strength = Medium

01 = Dithering on, Strength = Minimum

00 = Dithering is turned off

bit 19-18

BOOST[1:0]:

Bias

Current

Selection

for

All

ADCs

bits

(impacts achievable maximum sampling speed, see Table 5-2)

11 = All channels have current x 2

10 = All channels have current x 1 (default)

01 = All channels have current x 0.66

00 = All channels have current x 0.5

bit 17-16

PRE[1:0] Analog Master Clock (AMCLK) Prescaler Value bits

11 = AMCLK = MCLK/8

10 = AMCLK = MCLK/4

01 = AMCLK = MCLK/2

00 = AMCLK = MCLK (default)

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