MCP3919B datasheet(63/81 Pages) MICROCHIP

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DS20006995A-page 63

MCP3919B

bit 15

EN_CRCCOM: CRC-16 Checksum on Serial Communications Enable bit

1 = CRC-16 checksum is provided at the end of each communication sequence (therefore ,each com-

munication is longer); the CRC-16 message is the complete communication sequence (see

Section 6.9 “Securing Read Communications Through CRC-16 Checksum” for more details)

0 = Disabled (default)

bit 14

EN_INT: CRCREG Interrupt Function Enable bit

1 = The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin (DR) will

become logic low and stays logic low if a CRCREG checksum error happens. This interrupt is

cleared if the LOCK[7:0] value is made equal to the password value (0xA5).

0 = The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG[15:0] bits are

still calculated properly and can still be read in this mode. No interrupt is generated, even when a

CRCREG checksum error happens (default).

bit 13-12

Reserved: Keep equal to ‘0’ at all times

bit 11-3

Unimplemented: Read as ‘0’

bit 2-0

DRSTATUS[2:0]: Individual ADC Channel Data Ready Status bit

DRSTATUS[n] = 1 – Channel CHn data are not ready (default)

DRSTATUS[n] = 0 – Channel CHn data are ready. The status bit is set back to ‘1’ after reading the

STATUSCOM register. The status bit is not set back to ‘1’ by the read of the corresponding channel ADC data.

STATUSCOM REGISTER (CONTINUED)

MCP3919B データシート(PDF) 63 Page - Microchip Technology