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ADRF6655ACPZ-R7 データシート(PDF) 29 Page - Analog Devices |
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ADRF6655ACPZ-R7 データシート(HTML) 29 Page - Analog Devices |
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29 / 44 page ![]() ADRF6655 Rev. 0 | Page 29 of 44 REGISTER 4—CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL With R4[2:0] set to 100, the on-chip charge pump, PFD, and reference path control register is programmed as shown in Figure 74. The charge pump current is controlled by the base charge pump current (ICP, BASE) and the value of the charge pump current multiplier (ICP, MULT). The base charge pump current can be set using an internal or external resistor (according to DB18 of Register 4). When using an external resistor, the value of ICP, BASE can be varied according to [] 8 . 37 250 4 . 217 , − ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ × = Ω BASE CP I RSET (3) When using the internal resistor, the base charge pump current is 250 μA. The actual charge pump current can be programmed to be a multiple (1, 2, 3, or 4) of the charge pump base current. The multiplying value (ICP, MULT) is equal to 1 plus the value of Bit DB11 and Bit DB10 in Register 4. The PFD phase offset multiplier (θPFD,OFS), which is set by Bit DB16 to Bit DB12 of Register 4, causes the PLL to lock with a nominally fixed phase offset between the PFD reference signal and the divided-down VCO signal. This phase offset is used to linearize the PFD-to-CP transfer function and can improve fractional spurs. The magnitude of the phase offset is determined by MULT CP OFS PFD I , , 5 . 22 [deg] θ = ΔΦ Finally, the phase offset can be either positive or negative depending on the value of DB17 in Register 4. The reference frequency applied to the PFD can be manipulated using the internal reference path source. The external reference frequency applied can be internally scaled in frequency by 2×, 1×, 0.5×, or 0.25×. This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range. The ADRF6655 also provides a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode is to provide a lock-detect output to allow the user to verify when the PLL has locked to the target frequency. In addition, several other internal signals may be passed to the MUXOUT pin, as described in Figure 74. |
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