ADRF6655

Rev. 0 | Page 12 of 44

PLL CHARACTERISTIC

Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, loop filter = 1.5 kHz, unless

otherwise noted.

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

1k

10k

100k

1M

10M

100M

OFFSET FREQUENCY (kHz)

LO = 2275MHz

LO = 1100MHz

+25°C

–10°C

–40°C

+70°C

+85°C

Figure 22. Typical Fractional-N Phase Noise Plot

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQUENCY (MHz)

+25°C

–10°C

–40°C

+70°C

+85°C

Figure 23.10 kHz to 40 MHz Integrated Phase Noise vs. LO Frequency

025

TIME (ms)

–2500

2500

–2000

2000

–1500

1500

–1000

1000

–500

500

2.290G

1

1: 10ms 2.289999883GHz

10

Figure 24. Lock Time for 10 MHz Step with 1.5 kHz Loop Filter

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

1050

1250

1450

1650

1850

2050

2250

LO FREQUENCY (MHz)

1 × PFD OFFSET

2 × PFD OFFSET

4 × PFD OFFSET

+25°C

–40°C

+85°C

Figure 25. LO Reference/PFD Spurs vs. LO Frequency

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQUENCY (MHz)

+25°C

–40°C

+85°C

HIGH-SIDE LO

LOW-SIDE LO

Figure 26. Tuning Voltage vs. LO Frequency

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–40 –30 –20 –10

0

10

20

30

40

50

60

70

80

TEMPERATURE (°C)

LO = 1100MHz, IP3SET = 3.2V

LO = 2300MHz, IP3SET = 3.2V

LO =2300MHz, IP3SET = OPEN

Figure 27. VPTAT MUXOUT Voltage vs. Temperature