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ADRF6655ACPZ-R7 データシート(PDF) 31 Page - Analog Devices

部品番号 ADRF6655ACPZ-R7
部品情報  Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO
PDF  44 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADRF6655ACPZ-R7 データシート(HTML) 31 Page - Analog Devices

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ADRF6655
Rev. 0 | Page 31 of 44
REGISTER 5—LO PATH AND MIXER CONTROL
With R5[2:0] set to 101, the LO path and mixer control register
is programmed as shown in Figure 75.
The LO output driver can be enabled to allow the user to review
the performance of the internally applied LO through the LOP
and LON local oscillator input/output pins. The LO input/output
control allows the user to disconnect the internal LO signal and
apply an external LO signal to the LOP and LON local oscillator
input/output pins. A divide-by-2 or divide-by-3 prescaler can be
selected to divide the frequency of the externally or internally
applied oscillator signal before the mixer.
When using an external frequency, stable local oscillator signal
to commutate the mixer core, it is possible to shut down the PLL
circuitry through the PLL enable address (DB6) of Register 5.
The internal mixer can be disabled using the mixer bias enable
address (DB7) of Register 5.
Register 5 also provides access to the CDAC Distortion
Compensation Setting (DB11:DB8). CDAC control can allow
the user to optimize the internal linearization circuitry to enhance
IP3 performance for high frequency RF input signals.
CDAC3 CDAC2 CDAC1 CDAC0
00
0
0
00
0
1
MINIMUM
...
...
...
...
...
...
...
...
...
...
...
11
1
1
MAXIMUM
CDAC DISTORTION
COMPENSATION
SETTLING
LDRV
0
1
LO OUTPUT DRIVER
ENABLE
DRIVER OFF (RECOMMENDED)
DRIVER ON
LXL
0
1
LO IN/OUT CONTROL
LO OUTPUT
LO INPUT
LDIV
0
1
DIVIDE BY 3
DIVIDE BY 2
DIVIDE-BY-2 OR DIVIDE-BY-3
PLEN
0
1
DISABLE
ENABLE
PLL ENABLE
MBE
0
1
DISABLE
ENABLE
MIXER BIAS ENABLE
RESERVED
MIXER
BIAS
ENABLE
PLL
ENABLE
LO
DIV 2/3
LO
IN/OUT
CNTRL
LO OUTPUT
DRIVER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
DB7
MBE
DB6
DB5
DB4
DB3
DB11
CDAC3
DB10
CDAC2
DB9
CDAC1
DB8
CDAC0
PLEN
LDIV
LXL
LDRV
CDAC DISTORTION
COMPENSATION
SETTING
CONTROL BITS
00000
000
00
0
0
DB2
DB1
DB0
C3(1) C2(0) C1(1)
Figure 75. LO Path and Mixer Control Register (R5)



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