ADRF6655ACPZ-R7 datasheet(40/44 Pages) AD

40 / 44 page

ADRF6655

Rev. 0 | Page 40 of 44

Table 5. Evaluation Board Configuration Options

Component

Function

Default Condition

VCC, GND, IP3SET, CP,

VCO_LDO, VCC_LO,

VCC_RF, VCC_BB, LE,

CLK, DATA

Power supply, ground, and other test points.

Not applicable

R1, R6, R7, R8, R17,

R18, R24, R25, R26,

R29, R31, R32, R36

Power supply decoupling. Shorts or power supply decoupling resistors.

R1, R6, R7, R8 = 0 Ω (0402),

R17, R18 = 0 Ω (0402),

R24, R25, R26 = 0 Ω (0402),

R29, R31, R32 = 0 Ω (0402),

R36 = 0 Ω (0402)

C1, C2, C7, C8, C9,

C10, C11, C12, C16,

C17, C18, C19, C20,

C21, C22, C23, C24,

C25, C27, C28, C29,

C39, C41, C42, C43

The capacitors provide the required decoupling of the supply-related pins.

C1, C8, C10 = 100 pF (0402),

C2, C39, C41 = 10 μF (0603),

C7, C9, C11 = 0.1 μF (0402),

C12, C16, C18 = 100 pF (0402),

C21, C22, C24 = 100 pF (0402),

C17, C19, C20 = 0.1 μF (0402),

C23, C25, C27 = 0.1 μF (0402),

C28 = 10 μF (3216),

C29 = 0.1 μF (0402),

C42, C43 = 150 pF (0402)

C5, C6, T7, T8

External LO path. T7 and T8 provide different footprints for different LO

path transformer selections. C5 and C6 provide the necessary ac coupling.

C5, C6 = 1 nF (0402),

T7 = open (generic footprint),

T8 = TC1-1-13M+ (Mini-Circuits)

R61, C31, R16

REFIN input path. R61 provides a broadband 50 Ω termination followed

by C31, an ac coupling capacitor. R16 provides an external connectivity

to the MUXOUT feature described in Register 4.

R61 = 49.9 Ω (0402),

C31 = 1 nF (0402), R16 = 0 Ω (0402)

R2, R5, R9, R10, R13,

R37, R38, R62, R63,

R65, R72, C13, C14,

C15, C40

Loop Filter Component Options. A variety of loop filter topologies are

supported using component placements R9, R10, R13, R37, C13, C14,

C15, R65, and C40. R2 provides resistor programmability of the charge

pump current (see Register 4 description). R5, R38, R62, R63, and R72

provide connectivity options to numerous test points for engineering

evaluation purposes.

R2 = R5 = open, R9 = 270 Ω (0402),

R10 = 68 Ω (0402), R13 = 0 Ω (0402)

C13 = 47nF, C14 = 0.1μF,

C15 = 4.7μF (0805),

C40 = open (0402),

R37, R38, R62, R63, R65, R72 = 0 Ω (0402)

L1, L2, R43, R44,

R47, R48, R58, R59,

R73, R74, T3, T6,

C35, C36

IF output path. This is the default configuration of the evaluation board

for downconversion applications. R73 and R74 are populated for

appropriate balun interface. The default values support a TC4-1W+ 4-to-1

impedance ratio transformer with center tap bias connection through

R59. A differential IF output interface can be configured by populating C35

and C36 and omitting R47 and R48. When configuring for differential output

operation or when using an ac-coupled transformer, it is important to use L1

and L2 to provide dc bias to the IF output pins. For additional information,

see the Output Matching and Biasing section.

L1, L2 = open, R44, R58, = open,

R43, R47, R48 = 0 Ω (0402),

R59, R73, R74 = 0 Ω (0402),

T3 = TC4-1W+ (Mini-Circuits),

T6 = open, C35, C36 = open

C37, C38, T4, T5

RF input interface. T4 and T5 provide different footprints for different

RF path transformer selections. C37 and C38 provide the necessary ac

coupling. See the Input Matching section for additional information.

C37, C38 = 100 pF (0402),

T4 = TC1-1-13M+ (Mini-Circuits),

T5 = open

P1, R3, R30, R35,

R50, R51, R52,

R57, C32, C33, C34

Serial port interface. A 9-pin D-sub connector is provided for connecting to a

host PC or control hardware. RC filter networks are provided on CLK, DATA,

and LE lines to help clean up PC control signal wave shape. Test points are

provided for control interface debug. R3 provides a connection to the

MUXOUT for sensing lock detect through the P1 connector. See the Digital

Interfaces section for additional information.

P1 = 9-pin D-sub male,

R3 = 10 kΩ (0402),

R30, R35, R57 = 100 Ω (0402),

R50, R51, R52 = 1 kΩ (0402),

C32, C33, C34 = 330 pF (0402)

C3, R12, R27, R60, L3

IP3SET linearization feature. R27 and R60 provision for a resistive divider

network for providing nominal IP3SET voltage. Alternatively, the IP3SET

pin can be externally driven via the test point or directly connected to

the 3.3 V LDO (Pin 2, DECL1) using a 0 Ω resistor for R12 and a ferrite chip

inductor for L3. For additional information regarding this feature, see the

IP3SET Linearization Feature section.

C3 = 0.1 μF (0402), R12 = open,

R27, R60 = open, L3 = open

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