ADRF6655ACPZ-R7 datasheet(18/44 Pages) AD

18 / 44 page

ADRF6655

Rev. 0 | Page 18 of 44

V-to-I Converter

The differential RF input signal is applied to a pair of resistively

degenerated common-emitter stages, which converts the

differential input voltage to output currents. The input stage also

provides 50 Ω termination to the RF input port. The linearity

of this V-to-I stage can be optimized for a given frequency with

Pin IP3SET at the expense of power dissipation and noise figure.

An additional way of improving linearity without affecting

power dissipation or noise figure is provided by the CDAC

signal controlled by serial port interface (SPI).

Mixer Core

The mixer core, based on the Gilbert cell design of four cross-

connected transistors, takes the currents from the V-to-I stage

and mixes them with the LO signal. This mixer core can be used

as a downconvert mixer as is or as an upconvert mixer with an

off-chip matching network for a given frequency range.

DIGITAL INTERFACES

The ADRF6655 provides access to the many programmable

features available within the IC using a 3-wire SPI control

interface. The minimum delays and hold times are presented

in the timing diagram in Figure 2. The SPI interface provides

digital control of the internal PLL/VCO as well as several other

features related to the mixer core, on-chip referencing, and available

system monitoring functions. The MUXOUT pin provides access

to several output signals that can be selected via the SPI interface.

The available outputs are buffered, frequency-scaled versions of

the reference, a PLL lock-detect signal, and an internal voltage

that is proportional to the IC junction temperature. Details

regarding the register settings and initialization sequence are

included in the Register Structure section.

NC = NO CONNECT

VCC1

DECL1

GND

RSET

VSET

REFIN

EXTERNAL

REFERENCE

RF INPUT

MONITOR

OUTPUT

SPI

CONTROL

GND

MUXOUT

DECL2

VCC2

GND

INN

INP

ADRF6655

VCCMIX

GND

IP3SET

CHARGE PUMP

LOOP FILTER

+5V

GND

VCCV2I

GND

+5V

IF OUTPUT

MATCHING

BALUN AND BIAS

IF OUTPUT

+5V

RF INPUT

MATCHING

BALUN

Figure 52. Basic Circuit Connections

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