LAN9500AI datasheet(209/213 Pages) MICROCHIP

209 / 213 page

 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 209

LAN950x

APPENDIX A:

DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Revision Level and

Date

Section/Figure/Entry

Correction

DS00001875A

(01-07-15)

Replaces previous SMSC version Rev. 1.2 (07-15-11); package outlines replaced, Product

Information System page replaces “ordering information”, reel size changed from 4,000 to

3,000.

Table 1-1, “LAN950x Family

Differences,” on page 4

Added LAN9500A/LAN9500Ai low power 100uW

crystal support as differentiating factor.

Section 8.6, "Clock Circuit," on

page 204

Added new 100uW crystal specifications and circuit

diagram (LAN9500A/LAN9500Ai only). The section

is now split into two subsections, one for 300uW

crystals and the other for 100uW crystals.

Rev. 1.2 (07-15-11)

Ordering Information

Added tape and reel options.

Rev 1.2 (07-13-11)

FIGURE 4-1: Power Connections

on page 24

Substituted “u” and “ohm” for Greek symbols mu

and omega that were not properly displayed

because of font issues.

Section 8.5.7, "JTAG Timing," on

page 203

Added section.

Section 5.5.8.1, "TX Checksum

Calculation," on page 69

Added note stating TX Checksum calculation should

not be used for UDP packets under IPv6.

Rev. 1.1 (11-05-10)

Section 7.5.8, "EDPD NLP /

Crossover Time Configuration

Added new register with EDPD NLP and crossover

time configuration bits.

Table 7-6, “PHY Control and Status

Added register 16 to the register map

Section 5.6.7, "HP Auto-MDIX," on

page 76

Added note related to auto-MDIX crossover time

extension bit of the EDPD NLP / Crossover Time

Configuration Register.

Section 5.6.8.2, "Energy Detect

Power-Down (EDPD)," on page 78

Added extra paragraph describing the NLP

configuration bits of the EDPD NLP / Crossover

Time Configuration Register.

Section 7.5.9, "Mode Control/Status

Added note to EDPWRDOWN bit regarding NLP

configuration bits.

Rev. 1.0 (05-17-10)

Initial Release.

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