LAN9500AI datasheet(182/213 Pages) MICROCHIP

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LAN950x

DS00001875A-page 182

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7.5.8

EDPD NLP / CROSSOVER TIME CONFIGURATION REGISTER

This register is supported only by LAN9500A/LAN9500Ai.

Index (In Decimal):

Size:

16 bits

Bits

Description

Type

Default

EDPD TX NLP Enable

When in Energy Detect Power-Down (EDPD) mode (EDPWRDOWN=1), this

bit enables the transmission of single TX NLPs at the interval defined by the

EDPD TX NLP Interval Timer Select field.

0 = TX NLP disabled

1 = TX NLP enabled when in EDPD mode

R/W

14:13

EDPD TX NLP Interval Timer Select

When in Energy Detect Power-Down (EDPD) mode (EDPWRDOWN=1) and

EDPD TX NLP Enable is 1, this field defines the interval used to send single

TX NLPs.

00 = 1 second (default)

01 = 768 ms

10 = 512 ms

11 = 256 ms

R/W

00b

EDPD RX Single NLP Wake Enable

When in Energy Detect Power-Down (EDPD) mode (EDPWRDOWN=1), this

bit enables waking the PHY on reception of a single RX NLP.

0 = RX NLP wake disabled

1 = TX NLP wake enabled when in EDPD mode

R/W

11:10

EDPD RX NLP Max Interval Detect Select

When in Energy Detect Power-Down (EDPD) mode (EDPWRDOWN=1) and

EDPD RX Single NLP Wake Enable is 0, this field defines the maximum

interval for detecting two RX NLPs to wake from EDPD mode

00 = 64 ms (default)

01 = 256 ms

10 = 512 ms

11 = 1 second

R/W

00b

9:1

RESERVED

Extend Manual 10/100 Auto-MDIX Crossover Time

When Auto-MIDX is enabled and the PHY is in manual 10BASE-T or

100BASE-TX mode, setting this bit to 1 extends the crossover time by 1984

ms to allow linking to an auto-negotiation link partner PHY.

0 = crossover time extension disabled

1 = crossover time extension enabled (1984 ms)

R/W

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