LAN9500AI datasheet(184/213 Pages) MICROCHIP

184 / 213 page

LAN950x

DS00001875A-page 184

 2010 - 2015 Microchip Technology Inc.

7.5.10

SPECIAL MODES REGISTER

Index (In Decimal):

Size:

16 bits

Bits

Description

Type

Default

15:8

RESERVED

7:5

MODE

PHY Mode of operation. Refer to Table 7-7 for more details.

R/W

NASR

111b

4:0

PHYADD

PHY Address. The PHY Address is used for the SMI address.

R/W

NASR

00001b

TABLE 7-7:

MODE CONTROL

MODE

Mode Definitions

Default Register Bit Values

[13,12,8]

[8,7,6,5]

000b

10BASE-T Half Duplex. Auto-negotiation disabled.

000

N/A

001b

10BASE-T Full Duplex. Auto-negotiation disabled.

001

N/A

010b

100BASE-TX Half Duplex. Auto-negotiation disabled.

CRS is active during Transmit & Receive.

100

N/A

011b

100BASE-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

101

N/A

100b

100ase-TX Half Duplex is advertised. Auto-

negotiation enabled. CRS is active during Transmit &

Receive.

110

0100

101b

Repeater mode. Auto-negotiation enabled. 100BASE-

TX Half Duplex is advertised. CRS is active during

Receive.

110

0100

110b

RESERVED - Do not set the device in this mode.

N/A

111b

All capable. Auto-negotiation enabled.

X1X

1111

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