データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

LAN9500AI データシート(PDF) 185 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 185 Page - Microchip Technology

Back Button LAN9500AI Datasheet HTML 181Page - Microchip Technology LAN9500AI Datasheet HTML 182Page - Microchip Technology LAN9500AI Datasheet HTML 183Page - Microchip Technology LAN9500AI Datasheet HTML 184Page - Microchip Technology LAN9500AI Datasheet HTML 185Page - Microchip Technology LAN9500AI Datasheet HTML 186Page - Microchip Technology LAN9500AI Datasheet HTML 187Page - Microchip Technology LAN9500AI Datasheet HTML 188Page - Microchip Technology LAN9500AI Datasheet HTML 189Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 185 / 213 page
background image
 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 185
LAN950x
7.5.11
SPECIAL CONTROL/STATUS INDICATIONS REGISTER
Index (In Decimal):
27
Size:
16 bits
Bits
Description
Type
Default
15
Override AUTOMDIX_EN Strap
0 = AUTOMDIX_EN configuration strap enables or disables HP Auto MDIX
1 = Override AUTOMDIX_EN configuration strap. PHY Register 27.14 and
27.13 determine MDIX function
R/W
0b
14
Auto-MDIX Enable
Only effective when 27.15=1, otherwise ignored.
0 = Disable Auto-MDIX. 27.13 determines normal or reversed connection.
1 = Enable Auto-MDIX. 27.13 must be set to 0.
R/W
0b
13
Auto-MDIX State
Only effective when 27.15=1, otherwise ignored.
When 27.14 = 0 (manually set MDIX state):
0 = no crossover (TPO = output, TPI = input)
1 = crossover (TPO = input, TPI = output)
When 27.14 = 1 (automatic MDIX) this bit must be set to 0.
Do not use the combination 27.15=1, 27.14=1, 27.13=1.
R/W
0b
12:11
RESERVED
RO
-
10
VCOOFF_LP
Forces the Receive PLL 10M to lock on the reference clock at all times:
0 = Receive PLL 10M can lock on reference or line as needed (normal
operation).
1 = Receive PLL 10M is locked on the reference clock. In this mode 10M
data packets cannot be received.
R/W
NASR
0b
9:5
RESERVED
RO
-
4
XPOL
Polarity state of the 10BASE-T:
0 = Normal polarity
1 = Reversed polarity
RO
0b
3:0
RESERVED
RO
-



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com