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EPC635 データシート(PDF) 21 Page - Espros Photonics corp |
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EPC635 データシート(HTML) 21 Page - Espros Photonics corp |
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21 / 97 page  Part No. Description Pin No. Value Toler- ance Supply class VSC Comments Min. Typ. Max. C3 VDDA 22 - 42 10 μF ±20% VDDA Low ESR C1 VDDPXH 23 - 42 1 μF ±20% VDDPXH Ceramic X7R C5 VBS 38 - 42 1 μF ±20% VBS Ceramic X7R C9 VDDPLL 33 - 32 1 μF ±20% VDDPLL Ceramic X7R C12 VDD 6 - 39 1 μF ±20% VDD Ceramic X7R C14, C16 VDDIO 36 – 37, 9 - 40 1 μF ±20% VDDIO Ceramic X7R C4 VDDA 22 - 42 100 nF ±20% VDDA Ceramic X7R C6 VBS 38 - 42 100 nF ±20% VBS Ceramic X7R C22 VDDPLL 61 - 62 100 nF ±20% VDDPLL Ceramic X7R C2 VDDPXH 22 - 42 10 nF ±20% VDDPXH Ceramic X7R C11 VDD 6 - 39 10 nF ±20% VDD Ceramic X7R C13, C15 VDDIO 36 – 37, 9 - 40 10 nF ±20% VDDIO Ceramic X7R C7, C8 XTAL 30 – 32, 31 - 32 --- 18 pF 2 --- ±20% VDDPLL Ceramic NPO L1 VDDPLL --- 100 nH ±20% VDDPLL Inductor X1 XTAL 30 - 31 --- 4 MHz --- ±100ppm VDDPLL Quartz / Resonator R4 - R15 Bus termination 0 Ohm 10 Ohm 33 Ohm ±20% VDDIO Resistors R16, R17 I2C pull-up 1 kOhm ±20% VDDIO Resistors R18, R19 I2C address 10 kOhm ±20% VDDIO Resistors Table 10: Values of component related to epc635 chip (Figure 14) Notes: 1 All other components are application specific. 2 The capacitor value has to be selected according the crystal or resonator supplier's recommendation. 5.2. External Clock epc635 can be driven by an external 4MHz clock source connected to XTALIN_CLKIN input pin. XTALOUT output pin left unconnected. In- put clock signal levels must match VDDPLL/VSSPLL supply levels (Table 1). When the external clock source is coming from +2.5/3.3V voltage domain, a simple resistor divider circuit can be deployed to adjust the voltage levels. The following resistor values R26/R27 are recommended: 1kΩ/2.2kΩ with +2.5V voltage domain; 1kΩ/1.2kΩ with +3.3V voltage domain (see Figure 16). XTALOUT is not designed to drive external loads. Therefore, it is not recommended to use XTALOUT as a “buffered clock source” for an- other device in the application circuit. NC OSC PLL R27 2k2/1k2 VDDIO +2.5V/+3.3V R26 1k/1k External clock XTALOUT 60 XTALIN _CLKIN 59 VSSIO VSSIO epc635 Figure 16: Resistor divider to adjust external clock voltage levels to XTALIN_CLKIN IMPORTANT: The optical performance of the chip directly depends on the input clock precision/stability; therefore, only a clean, stable clock must be used as external clock source. © 2017 ESPROS Photonics Corporation Characteristics subject to change without notice 21 / 97 Datasheet_epc635-V1.02 www.espros.com |
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