EPC635 datasheet(39/97 Pages) EPC

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5.9.2. Single or continuous measurement control

Single measurement control

The selected measurement mode (4x DCS, 2x DCS, grayscale, …) defines, how many frames the chip performs by the stimulation of one

SHUTTER pulse for a measurement cycle. This pulse can be applied either by the HW SHUTTER pin or by SW control of the shutter_en

bit. Whereas the SW controlled SHUTTER is auto-cleared after propagation, the HW Shutter needs a minimum hold time of 250ns and

must be set back manually latest before the HSYNC_A1 signal of the last row pair of the last DCS frame (last HSYNC_A1 of the last

frame).

During such a measurement cycle, the next frame acquisition starts immediately after the last data readout on the TCMI interface until all

frames are performed.

Continuous measurement control (auto-run)

As long as in the Shutter_Control register the multi_frame_en = 1 is set or the HW SHUTTER is applied during the readout of the last row

pair of the last frame, the epc635 runs in a non-stop measurement mode. The chip starts immediately next measurement cycle if the actual

one is terminated (Figure 43). If the trigger arrives before the readout of the last row pair of the last frame, then it is ignored.

5.9.3. TCMI data format

TCMI supports three 8 bit transfer formats:

■ msb/lsb split mode:

Transfers 12 bit pixel data with MSByte leading and LSByte trailing with 2x DCLK.

Refer to Table 17 and Figure 36.

■ lsb/msb split mode:

Transfers 12 bit pixel data with LSByte leading and MSByte trailing with 2x DCLK.

Refer to Table 18 and Figure 37.

■ 8-bit mode:

Transfers the 8 MSB bits of the pixel data with 1x DCLK.

Refer to Table 19 and Figure 38).

The three modes require lines DATA[7:0] to be connected in the application. The TCMI data format can be selected in the register

I2C_TCMI_control. tcmi_data_format_sel (refer to I2C_TCMI_ register).

IMPORTANT: The application should not set tcmi_data_format_sel = 00.

The two split modes transmit pixel values in two consecutive DCLK cycles. As a result HSYNC time is doubled. When 8 bit precision is

enough, the application should use 8-bit mode and set the DCLK to half of the speed (e.g.: 10MHz instead of 20MHz default). This way,

the overall DCS frame transfer time remains like in split modes and frame rate is not reduced.

1st Byte: MSByte

2nd Byte: LSByte

b11

b10

SAT

Table 17: TCMI msb/lsb split mode, HW synchronization data format

1st Byte: LSByte

2nd Byte: MSByte

SAT

b11

b10

Table 18: TCMI lsb/msb split mode, HW synchronization data format

Byte

b11

b10

Table 19: TCMI 8-bit mode , HW synchronization data format

TCMI data formats can be combined with the ADC conversion speed up. Refer to chapter 5.7.2 for ADC resolution v.s. conversion time

setting (DC_ramp.adc_res_sel, ADC_ramp.adc_numlsb_sel and SIR_hi/lo registers).

The saturation flag can be optionally inserted into the DATA[0] of the LSByte by setting tcmi_8bit_data_sat_en = 1 during the 1. or 2.

DCLK cycle for the msb/lsb or lsb/msb split modes, respectively. This feature is not available for the 8-bit mode. In this case either the

XSYNC_SAT_CFG pin can be used along with the DATA[*] pins or the tcmi_data_sat_en = 1 must be set to force all DATA[*] = 0xFFF

when the corresponding pixel is saturated.

Characteristics subject to change without notice

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