EPC635 datasheet(83/97 Pages) EPC

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8.7.4. TCMI_CLK_divider

TCMI_CLK_divider

CGU register, SEG0.*: TCMI clock

0x89

Bit No.

Bit name

dclk_skew

_en

reserved

tcmi_clk_div

Operation

Default

0x03

dclk_skew_en:

DCLK skew enable

0: disable

1: enable

Note1: Use dclk_skew_en = 1 to delay DCLK edge (typ. 2ns) to compensate PCB delays.

Might be particularly useful when tcmi_clk_div = 0 (divide by 1).

When set normal, DCLK edge is centered with respect to other TCMI *SYNC*, DATA[7:0] outputs.

tcmi_clk_div:

Provides the clock to the TCMI by integer division of the PLL clock.

Default = 1: ftcmi_clk = 80MHz / (tcmi_clk_div + 1) = 80MHz / 4 = 20MHz

8.7.5. Demodulation_delays

Demodulation_delays

Mod./demod. registers, SEG1 *: Delays

0x8B

Bit No.

Bit name

reserved

mgx_del_sel

Operation

Default

0x01

mgx_del_sel:

Number of pll_clk period delays on the abd, abg, mga, mgb signals in order to compensate internal LED driver

delay (all modulation modes)

no delay

1 clock

2 clocks

…

12:

12 clocks

13 … 15: reserved

Note 1: When DLL is enabled, mgx_del_sel must be initialized to a higher value with respect to the external

LED/LD circuit's initial delay + max. delay deviation over the system's operating conditions.

Minimum recommendation: 2.

Note 2: When mgx_del_sel set > 12 (i.e. 13, 14 or 15), delay is internally limited to 12 pll_clk periods.

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

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