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EPC635 データシート(PDF) 11 Page - Espros Photonics corp |
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EPC635 データシート(HTML) 11 Page - Espros Photonics corp |
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11 / 97 page  Pin No. Pin name Supply class VSC Pin type Rst func Rst level Description Analog pins 26 LED VDDLED AOD VLED max LED/LD driver open-drain output 3 24 LEDFB VDDLED AI VLEDFB max LED/LD driver feedback input 3 20 PIN20 --- --- Reserved. Connect to VSSA with 10 kOhm 21 PIN21 --- --- Reserved. Connect to VSSA with 10 kOhm 43 PIN43 VDDPXH AI Reserved. Do not any electrical connection ex- cept to a test pad (suggested). 44 PIN44 VDDPXH AI Reserved. Do not any electrical connection ex- cept to a test pad (suggested). Supply pins, digital 36 VDDIO1 VDDIO PWR IO supply VDDIO 9 VDDIO2 VDDIO PWR IO supply VDDIO 6 VDD VDD PWR Digital supply VDD 33 VDDPLL VDDPLL PWR PLL supply 37 VSSIO1 VDDIO GND IO ground VSSIO 40 VSSIO2 VDDIO GND IO ground VSSIO 41 VSSIO3 VDDIO GND IO ground VSSIO 39 VSS VDD GND Digital ground VSS 32 VSSPLL VDDPLL GND PLL ground Supply pins, analog 22 VDDA VDDA PWR Analog supply VDDA 38 VBS VBS PWR Bias supply 23 VDDPXH VDDPXH PWR Pixel analog 2 supply VDDPXH 42 VSSA VDDA GND Analog ground VSSA 25 VSSLED VDDLED GND LED/LD driver ground (return current) 2 Table 8 cont.: Pin list Notes: 1 DIO pin is configured as input with internal pull-down resistor enabled during RESET = 0 (active), only. As soon as RESET is driven to 1, pins stay in that state for another 4x osc_clk periods (see chapter 5.3.3., Strap pins), then the pin is configured as output, finally the in- ternal pull-down resistor is disabled. From this moment on, the pin can be used for normal output function. 2 VSSLED is the dedicated, isolated GND pin for the LED/LD return-current from external circuitry. It must be connected to PCB GND plane together with the other VSSA GND pins. 3 LED output can be used to drive an external amplifier with an addition of a pull-up resistor. The voltages at LED output and LEDFB input pins must not exceed values in Table 1: Operating conditions and electrical characteristics. LED2 output is a push-pull driver for delivering symmetric rise/fall times to the external LED driver circuit. LED2 is internally connected to VDDIO/VSSIO supplies. During integration time, all TCMI pins are silent except for DCLK. As a result, LED2 pin will not pick up switch - ing noise from all other TCMI pins. This can be avoided by using gated DCLK mode. When the TCMI interface is slowed down by setting DCLK <= 10MHz, data-out phase of the last two rows may overlap with the next frame's integration time as another noise source (for very short integration times <100µs). This can be avoided by SEQ_Control.pixel_seq_wait_row_done_en = 1 (default) with a small re- duction on the frame rate. LED and LED2 must not be used simultaneously for driving LED circuits on the PCB. They exhibit different insertion delays and may cause unpredicted distance offset/measurement results. 4 RESET pin has a 600kΩ (typical) internal pull-down resistor. Therefore, this pin can be safely connected to a standard GPIO of a CPU which is initially high-Z or open-drain during power up sequence. Once the SW takes control, it can program this GPIO as output and drive 1 to release the RESET. The internal pull-down can be override by and external 10kΩ pull-up and a series capacitor to build a sim- ple delayed power-on reset for evaluation/qualification purposes. 5 I2C pins SCL, SDA are according to I2C standards. They are I2C slave pins which need external pull-up resistors on the PCB. Values of R1 and R2 in the schematics are given only for indicative purposes and must be re-calculated according to the total capacitive load of all I2C slave/master devices and operating mode (FM or FM+) of the I2C (chapter 5.4.) in the application. © 2017 ESPROS Photonics Corporation Characteristics subject to change without notice 11 / 97 Datasheet_epc635-V1.02 www.espros.com |
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