EPC635 datasheet(31/97 Pages) EPC

31 / 97 page

Figure 27 shows the example for 4x DCS frames and a DLL_measurement_rate = 4.

Start &

init

Integration

DCS0

Conversion &

read-out DCS0

Integration

DCS1

Conversion &

read-out DCS1

Integration

DCS2

Conversion &

read-out DCS2

Integration

DCS3

Conversion &

read-out DCS3

Task

LED modulation

OFF

SYNCH

Total measurement cycle t

CYCLE

Integration time t

INT

Figure 27: DLL synchronization example for 4x DCS frames

The DLL period tSYNCH is skipped for DLL_measurement_rate = 0. The last compensation delay value is preserved.

Design notes:

■ Minimize the path delay from the feedback node in the resistor divider to the LEDFB pin (yellow).

■ Place the resistor dividers as close as possible to the LEDFB pin on the PCB.

■ Noisy circuits should be placed away from the LEDFB pin and resistor dividers.

5.6.1. DLL locking operation

Before starting the DLL locking operation, the mga_ref signal must be delayed behind the led_fb signal (see Figure 28) by setting mgx_de-

lay_sel = 1 or higher in the register Demodulation_delays. It gives an initial 12.5ns phase offset to the mga_ref signal. Next, the modulator

toggles the mgx and led_mod signals without enabling the DLL (DLL pre-synchronization: DLL_en_del). Finally, the modulator enables the

DLL locking operation with mgx and led_mod signals toggling until the end (DLL_en).

The default DLL pre-synchronization is 10µs and DLL lock time 30µs. It is indicated as tSYNC in Figure 27. These values can be changed by

DLL_en_del/DLL_en registers (see Table 41 , DLL Synchronization registers).

led_mod

mga

pll_clk

mga_ref

mgx_del_sel

mga_ref

led_fb: after delay locked

led_fb: before delay locked

mga_ref must be delayed behind the led_fb

before DLL starts locking operation

Delay locked

n-Clk Delay

PLL

= 12.5ns

x-Delay

led_fb

DLL

Figure 28: DLL delay locking operation

If locked, the compensation delay is frozen (x-Delay) and the mgx and led_mod signals are in phase (point A and B) until next synchroniz -

ation cycle. Set the DLL synchronization rate (DLL_measurement_rate register) in multiples of the DCS frame number. Example: Set

DLL_measurement_rate = 4 if the system runs the 4x DCS mode (dcs_sel = 11 in the MOD_Control.dcs_sel register). All DCS frames (0-

3) are acquired this way with the same DLL compensation delay and the samples stay correlated with each other.

DLL_measurement_rate = 0: Holds last compensation delay and uses it for the next DCS frames.

IMPORTANT:

■ The DLL has a delay locking range of 6ns ... 76ns with 7ps fine delay steps.

■ When the DLL is enabled, mgx_del_sel must be 1 or higher because in addition to the delays from the LED driver, LED/LD circuit and

LEDFB input a minimum 6ns delay is inserted on the led_mod line.

■ The value of the mgx_del_sel register must be > 1 if the delay variation of LEDF signal is more than one pll_clk period. This allows to

compensate this wide-range variation, e.g. for LED/LD circuits placed far away from the epc635 and causing long time offsets.

Characteristics subject to change without notice

31 / 97

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