ADXL346ACCZ-R2 datasheet(25/40 Pages) AD

25 / 40 page

Data Sheet

ADXL346

When clearing the link bit, it is recommended that the part be

placed into standby mode and then set back to measurement

mode with a subsequent write. This is done to ensure that the

device is properly biased if sleep mode is manually disabled;

otherwise, the first few samples of data after the link bit is cleared

may have additional noise, especially if the device was asleep

when the bit was cleared.

AUTO_SLEEP Bit

If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables

the autosleep functionality. In this mode, the ADXL346 auto-

matically switches to sleep mode if the inactivity function is

enabled and inactivity is detected (that is, when acceleration is

below the THRESH_INACT value for at least the time indicated

by TIME_INACT). If activity is also enabled, the ADXL346

automatically wakes up from sleep after detecting activity and

returns to operation at the output data rate set in the BW_RATE

switching to sleep mode. See the description of the sleep bit in this

section for more information on sleep mode.

If the link bit is not set, the AUTO_SLEEP feature is disabled,

and setting the AUTO_SLEEP bit does not have any impact on

device operation. Refer to the Link Bit section or the Link Mode

section for more information about using the link feature.

When clearing the AUTO_SLEEP bit, it is recommended that the

part be placed into standby mode and then set back to measure-

ment mode with a subsequent write. This is done to ensure that

the device is properly biased if sleep mode is manually disabled;

otherwise, the first few samples of data after the AUTO_SLEEP

bit is cleared may have additional noise, especially if the device

was asleep when the bit was cleared.

Measure Bit

A setting of 0 in the measure bit places the part into standby mode,

and a setting of 1 places the part into measurement mode. The

ADXL346 powers up in standby mode with minimum power

consumption.

Sleep Bit

A setting of 0 in the sleep bit puts the part into the normal mode

of operation, and a setting of 1 places the part into sleep mode.

Sleep mode suppresses DATA_READY, stops transmission of data

to FIFO, and switches the sampling rate to one specified by the

wakeup bits. In sleep mode, only the activity function can be used.

While the DATA_READY interrupt is suppressed, the output

data registers are still updated at the sampling rate set by the

wakeup bits.

When clearing the sleep bit, it is recommended that the part be

placed into standby mode and then set back to measurement

mode with a subsequent write. This is done to ensure that the

device is properly biased if sleep mode is manually disabled;

otherwise, the first few samples of data after the sleep bit is

cleared may have additional noise, especially if the device was

asleep when the bit was cleared.

Wakeup Bits

These bits control the frequency of readings in sleep mode as

described in Table 20.

Table 20. Frequency of Readings in Sleep Mode

Setting

Frequency (Hz)

DATA_READY

SINGLE_TAP

DOUBLE_TAP

Activity

Inactivity

FREE_FALL

Watermark

Overrun/

orientation

Setting bits in this register to a value of 1 enables their respective

functions to generate interrupts, whereas a value of 0 prevents

the functions from generating interrupts. The DATA_READY,

watermark, and overrun/orientation bits enable only the interrupt

output; the functions are always enabled. It is recommended that

interrupts be configured before enabling their outputs.

DATA_READY

SINGLE_TAP

DOUBLE_TAP

Activity

Inactivity

FREE_FALL

Watermark

Overrun/

orientation

Bits set to 0 in this register send their respective interrupts to the

INT1 pin, whereas bits set to 1 send their respective interrupts to

the INT2 pin. All selected interrupts for a given pin are OR’ed.

DATA_READY

SINGLE_TAP

DOUBLE_TAP

Activity

Inactivity

FREE_FALL

Watermark

Overrun/

orientation

Bits set to 1 in this register indicate that their respective functions

have triggered an event, whereas bits set to 0 indicate that the

corresponding events have not occurred. The DATA_READY,

watermark, and overrun/orientation bits are always set if the

corresponding events occur, regardless of the INT_ENABLE

DATAX, DATAY, and DATAZ registers. The DATA_READY and

watermark bits may require multiple reads, as indicated in the

FIFO mode descriptions in the FIFO section. Other bits, and the

corresponding interrupts, including orientation if enabled, are

cleared by reading the INT_SOURCE register.

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