ADXL346ACCZ-R2 datasheet(14/40 Pages) AD

14 / 40 page

ADXL346

Data Sheet

Rev. C | Page 14 of 40

SERIAL COMMUNICATIONS

I2C and SPI digital communications are available. In both cases,

the ADXL346 operates as a slave. I2C mode is enabled if the CS pin

is tied high to VDD I/O. The CS pin should always be tied high to

VDD I/O or be driven by an external controller because there is no

default mode if the CS pin is left unconnected. Therefore, not

taking these precautions may result in an inability to communicate

with the part. In SPI mode, the CS pin is controlled by the bus

master. In both SPI and I2C modes of operation, data transmitted

from the ADXL346 to the master device should be ignored during

writes to the ADXL346.

SPI

For SPI, either 3- or 4-wire configuration is possible, as shown in

the connection diagrams in Figure 34 and Figure 35. Clearing the

SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)

selects 4-wire mode, whereas setting the SPI bit selects 3-wire

mode. The maximum SPI clock speed is 5 MHz with 100 pF

maximum loading, and the timing scheme follows clock polarity

(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to

the ADXL346 before the clock polarity and phase of the host

processor are configured, the CS pin should be brought high

before changing the clock polarity and phase. When using 3-wire

SPI, it is recommended that the SDO pin either be pulled up to

VDD I/O or be pulled down to GND via a 10 kΩ resistor.

PROCESSOR

D OUT

D IN/OUT

D OUT

ADXL346

SDIO

SDO

SCLK

Figure 34. 3-Wire SPI Connection Diagram

PROCESSOR

D OUT

D IN

D OUT

ADXL346

SDI

SDO

SCLK

Figure 35. 4-Wire SPI Connection Diagram

CS is the serial port enable line and is controlled by the SPI

master. This line must go low at the start of a transmission and

high at the end of a transmission, as shown in Figure 37. SCLK

is the serial port clock and is supplied by the SPI master. SCLK

should idle high during a period of no transmission. SDI and

SDO are the serial data input and output, respectively. Data is

updated on the falling edge of SCLK and should be sampled on

the rising edge of SCLK.

To read or write multiple bytes in a single transmission, the

multiple-byte bit, located after the R/W bit in the first byte transfer

(MB in Figure 37 to Figure 39), must be set. After the register

addressing and the first byte of data, each subsequent set of

clock pulses (eight clock pulses) causes the ADXL346 to point to

the next register for a read or write. This shifting continues until

the clock pulses cease and CS is deasserted. To perform reads or

writes on different, nonsequential registers, CS must be

deasserted between transmissions and the new register must be

addressed separately.

The timing diagram for 3-wire SPI reads or writes is shown in

Figure 39. The 4-wire equivalents for SPI writes and reads are

shown in Figure 37 and Figure 38, respectively. For correct

operation of the part, the logic thresholds and timing parameters

in Table 9 and Table 10 must be met at all times.

Use of the 3200 Hz and 1600 Hz output data rates is recom-

mended only with SPI communication rates greater than or

equal to 2 MHz. The 800 Hz output data rate is recommended

only for communication speeds greater than or equal to 400 kHz,

and the remaining data rates scale proportionally. For example,

the minimum recommended communication speed for a 200 Hz

output data rate is 100 kHz. Operation at an output data rate

above the recommended maximum may result in undesirable

effects on the acceleration data, including missing samples or

additional noise.

Preventing Bus Traffic Errors

The ADXL346 CS pin is used both for initiating SPI transactions,

and for enabling I2C mode. When the ADXL346 is used on a SPI

bus with multiple devices, its CS pin is held high while the master

communicates with the other devices. There may be conditions

where a SPI command transmitted to another device looks like

a valid I2C command. In this case, the ADXL346 would interpret

this as an attempt to communicate in I2C mode, and could inter-

fere with other bus traffic. Unless bus traffic can be adequately

controlled to assure such a condition never occurs, it is recom-

mended to add a logic gate in front of the SDI pin as shown in

Figure 36. This OR gate will hold the SDA line high when CS is

high to prevent SPI bus traffic at the ADXL346 from appearing

as an I2C start command.

PROCESSOR

D OUT

D IN

D OUT

ADXL346

SDI

SDO

SCLK

Figure 36. Recommended SPI Connection Diagram when Using Multiple SPI

Devices on a Single Bus

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