ADXL346ACCZ-R2 datasheet(27/40 Pages) AD

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Data Sheet

ADXL346

FIFO_TRIG

Entries

FIFO_TRIG Bit

A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,

and a 0 means that a FIFO trigger event has not occurred.

Entries Bits

These bits report how many data values are stored in FIFO.

Access to collect the data from FIFO is provided through the

DATAX, DATAY, and DATAZ registers. FIFO reads must be

done in burst or multiple-byte mode because each FIFO level is

cleared after any read (single- or multiple-byte) of FIFO. FIFO

stores a maximum of 32 entries, which equates to a maximum

of 33 entries available at any given time because an additional

entry is available at the output filter of the device.

XSIGN

YSIGN

ZSIGN

XTAP

YTAP

ZTAP

xSIGN Bits

These bits indicate the sign of the first axis involved in a tap

event. A setting of 1 corresponds to acceleration in the negative

direction, and a setting of 0 corresponds to acceleration in the

positive direction. These bits update only when a new single-

tap/double-tap event is detected, and only the axes enabled in the

TAP_AXES register (Address 0x2A) are updated. The TAP_SIGN

Sign section for more details.

xTAP Bits

These bits indicate the first axis involved in a tap event. A

setting of 1 corresponds to involvement in the event, and a

setting of 0 corresponds to no involvement. When new data is

available, these bits are not cleared but are overwritten by the

new data. The TAP_SIGN register should be read before clearing

the interrupt. Disabling an axis from participation clears the

corresponding source bit when the next single-tap/double-tap

event occurs.

INT_

ORIENT

Dead zone

INT_

Divisor

INT_ORIENT Bit

Setting the INT_ORIENT bit enables the orientation interrupt.

A value of 1 overrides the overrun function of the device and

replaces overrun in the INT_MAP (Address 0x2F), INT_ENABLE

(Address 0x2E), and INT_SOURCE (Address 0x30) registers with

the orientation function. After setting the INT_ORIENT bit, the

orientation bits in the INT_MAP and INT_ENABLE registers must

be configured to map the orientation interrupt to INT1 or INT2

and to enable generation of the interrupt to the pin.

An orientation interrupt is generated whenever the orientation

status for the mode selected by the INT_3D bit changes in the

orient register (Address 0x3C). The orientation interrupt is

cleared by reading the INT_SOURCE register. Clearing the

INT_ORIENT bit, or the orientation bit in the INT_ENABLE

Writing to the BW_RATE register (Address 0x2C) or placing

the part into standby mode resets the orientation feature, clearing

the orientation filter and the interrupt. However, resetting the

orientation feature also resets the orientation status in the orient

generated when the next output sample is available if the present

orientation is not the default orientation. A value of 0 for the

INT_ORIENT bit disables generation of the orientation interrupt

and permits the use of the overrun function.

Dead Zone Bits

These bits determine the region between two adjacent orientations,

where the orientation is considered invalid and is not updated. A

value of 0 may result in undesirable behavior when the orientation

is close to the bisector between two adjacent regions. The dead zone

angle is determined by these bits, as described in Table 24. See the

Orientation Sensing section for more details.

Table 24. Dead Zone and Divisor Codes

Decimal

Binary

Dead Zone Angle

(Degrees)

Divisor

Bandwidth (Hz)

000

5.1

ODR/9

001

10.2

ODR/22

010

15.2

ODR/50

011

20.4

ODR/100

100

25.5

ODR/200

101

30.8

ODR/400

110

36.1

ODR/800

111

41.4

ODR/1600

INT_3D Bit

If the orientation interrupt is enabled, the INT_3D bit determines

whether 2D or 3D orientation detection generates an interrupt.

A value of 0 generates an interrupt only if the 2D orientation

changes from a valid 2D orientation to a different valid 2D

orientation. A value of 1 generates an interrupt only if the 3D

orientation changes from a valid 3D orientation to a different

valid 3D orientation.

Divisor Bits

These bits set the bandwidth of the filter used to low-pass filter the

measured acceleration for stable orientation sensing. The divisor

bandwidth is determined by these bits, as detailed in Table 24,

where ODR is the output data rate set in the BW_RATE register

(Address 0x2C). See the Orientation Sensing section for more

details.

Rev. C | Page 27 of 40

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