ADXL346ACCZ-R2 datasheet(17/40 Pages) AD

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Data Sheet

ADXL346

I2C

With CS tied high to VDD I/O, the ADXL346 is in I2C mode,

requiring a simple 2-wire connection as shown in Figure 40.

The ADXL346 conforms to the UM10204 I2

C-Bus Specification

and User Manual, Rev. 03—19 June 2007, available from NXP

Semiconductors. It supports standard (100 kHz) and fast (400 kHz)

data transfer modes if the bus parameters given in Table 11 and

Table 12 are met. Single- or multiple-byte reads/writes are sup-

ported, as shown in Figure 41. With the ALT ADDRESS pin (Pin

7) high, the 7-bit I2C address for the device is 0x1D, followed by

the R/W bit. This translates to 0x3A for a write and 0x3B for a

read. An alternate I2C address of 0x53 (followed by the R/W bit)

can be chosen by grounding the ALT ADDRESS pin. This

translates to 0xA6 for a write and 0xA7 for a read.

There are no internal pull-up or pull-down resistors for any

unused pins; therefore, there is no known state or default state

for the CS or ALT ADDRESS pin if left floating or unconnected.

It is required that the CS pin be connected to VDD I/O and that

the ALT ADDRESS pin be connected to either VDD I/O or GND

when using I2C.

Due to communication speed limitations, the maximum output

data rate when using 400 kHz I2C is 800 Hz and scales linearly with

a change in the I2C communication speed. For example, using I2C

at 100 kHz would limit the maximum ODR to 200 Hz. Operation

at an output data rate above the recommended maximum may

result in an undesirable effect on the acceleration data, including

missing samples or additional noise.

PROCESSOR

D IN/OUT

D OUT

VDD I/O

ADXL346

SDA

ALT ADDRESS

SCL

Figure 40. I2C Connection Diagram (Address 0x53)

If other devices are connected to the same I2C bus, the nominal

operating voltage level of these other devices cannot exceed VDDI/O

by more than 0.3 V. External pull-up resistors, RP, are necessary for

proper I2C operation. Refer to the UM10204 I2C-Bus Specification

and User Manual, Rev. 03—19 June 2007, when selecting pull-up

resistor values to ensure proper operation.

Table 11. I2C Digital Input/Output

Limit1

Parameter

Test Conditions

Min

Max

Unit

Digital Input

Low Level Input Voltage (VIL)

0.3 × VDD I/O

High Level Input Voltage (VIH)

0.7 × VDD I/O

Low Level Input Current (IIL)

VIN = VDD I/O

0.1

µA

High Level Input Current (IIH)

VIN = 0 V

−0.1

µA

Digital Output

Low Level Output Voltage (VOL)

VDD I/O < 2 V, IOL = 3 mA

0.2 × VDD I/O

VDD I/O ≥ 2 V, IOL = 3 mA

400

Low Level Output Current (IOL)

VOL = VOL, max

Pin Capacitance

fIN = 1 MHz, VIN = 2.6 V

Limits are based on characterization results; not production tested.

1THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

MASTER START

SLAVE ADDRESS + WRITE

SLAVE

ACK

MASTER START

SLAVE ADDRESS + WRITE

SLAVE

ACK

MASTER START

SLAVE ADDRESS + WRITE

STOP

SLAVE

ACK

MASTER START

START1

SLAVE ADDRESS + WRITE

NACK

STOP

SLAVE

ACK

DATA

STOP

ACK

SINGLE-BYTE WRITE

MULTIPLE-BYTE WRITE

DATA

MULTIPLE-BYTE READ

SLAVE ADDRESS + READ

ACK

DATA

STOP

NACK

ACK

SINGLE-BYTE READ

Figure 41. I2C Device Addressing

Rev. C | Page 17 of 40

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