ADXL346ACCZ-R2 datasheet(26/40 Pages) AD

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ADXL346

Data Sheet

SELF_TEST

SPI

INT_INVERT

FULL_RES

Justify

Range

The DATA_FORMAT register controls the presentation of data

to Register 0x32 through Register 0x37. All data, except that for

the ±16 g range, must be clipped to avoid rollover.

SELF_TEST Bit

A setting of 1 in the SELF_TEST bit applies a self-test force to

the sensor, causing a shift in the output data. A value of 0 disables

the self-test force.

SPI Bit

A value of 1 in the SPI bit sets the device to 3-wire SPI mode,

and a value of 0 sets the device to 4-wire SPI mode.

INT_INVERT Bit

A value of 0 in the INT_INVERT bit sets the interrupts to active

high, and a value of 1 sets the interrupts to active low.

FULL_RES Bit

When this bit is set to a value of 1, the device is in full resolution

mode, where the output resolution increases with the g range

set by the range bits to maintain a 4 mg/LSB scale factor. When

the FULL_RES bit is set to 0, the device is in 10-bit mode, and

the range bits determine the maximum g range and scale factor.

Justify Bit

A setting of 1 in the justify bit selects left-justified (MSB) mode,

and a setting of 0 selects right-justified mode with sign extension.

Range Bits

These bits set the g range as described in Table 21.

Table 21. g Range Setting

Setting

g Range

±2 g

±4 g

±8 g

±16 g

DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)

These six bytes (Register 0x32 to Register 0x37) are eight bits

each and hold the output data for each axis. Register 0x32 and

and Register 0x37 hold the output data for the z-axis. The output

data is twos complement, with DATAx0 as the least significant byte

and DATAx1 as the most significant byte, where x represents X,

Y, or Z. The DATA_FORMAT register (Address 0x31) controls

the format of the data. It is recommended that a multiple-byte

read of all registers be performed to prevent a change in data

between reads of sequential registers.

FIFO_MODE

Trigger

Samples

FIFO_MODE Bits

These bits set the FIFO mode, as described in Table 22.

Table 22. FIFO Modes

Setting

Mode

Function

Bypass

FIFO is bypassed.

FIFO

FIFO collects up to 32 values and then

stops collecting data, collecting new

data only when FIFO is not full.

Stream

FIFO holds the last 32 data values.

When FIFO is full, the oldest data is

overwritten with newer data.

Trigger

When triggered by the trigger bit,

FIFO holds the last data samples

before the trigger event and then

continues to collect data until FIFO is

full. New data is collected only when

FIFO is not full.

Trigger Bit

A value of 0 in the trigger bit links the trigger event of trigger mode

to INT1, and a value of 1 links the trigger event to INT2.

Samples Bits

The function of these bits depends on the FIFO mode selected (see

Table 23). Entering a value of 0 in the samples bits immediately

sets the watermark bit in the INT_SOURCE register (Address

0x30), regardless of which FIFO mode is selected. Undesirable

operation may occur if a value of 0 is used for the samples bits

when trigger mode is used.

Table 23. Samples Bits Functions

FIFO Mode

Samples Bits Function

Bypass

None.

FIFO

Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Stream

Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Trigger

Specifies how many FIFO samples are retained in

the FIFO buffer before a trigger event.

Rev. C | Page 26 of 40

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