ADXL346

Data Sheet

Rev. C | Page 18 of 40

Table 12. I2C Timing (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)

Limit1, 2

Parameter

Min

Max

Unit

Description

fSCL

400

kHz

SCL clock frequency

t1

2.5

μs

SCL cycle time

t2

0.6

μs

tHIGH, SCL high time

t3

1.3

μs

tLOW, SCL low time

t4

0.6

μs

tHD, STA, start/repeated start condition hold time

t5

100

ns

tSU, DAT, data setup time

t63, 4, 5, 6

0

0.9

μs

tHD, DAT, data hold time

t7

0.6

μs

tSU, STA, setup time for repeated start

t8

0.6

μs

tSU, STO, stop condition setup time

t9

1.3

μs

tBUF, bus-free time between a stop condition and a start condition

t10

300

ns

tR, rise time of both SCL and SDA when receiving

0

ns

tR, rise time of both SCL and SDA when receiving or transmitting

t11

300

ns

tF, fall time of SDA when receiving

250

ns

tF, fall time of both SCL and SDA when transmitting

CB

400

pF

Capacitive load for each bus line

1 Limits are based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.

2 All values referred to the VIH and the VIL levels given in Table 11.

3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.

4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH,min of the SCL signal) to bridge the undefined region of

the falling edge of SCL.

5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.

6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min).

SDA

t9

SCL

t3

t10

t11

t4

t4

t6

t2

t5

t7

t1

t8

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

Figure 42. I2C Timing Diagram