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STV2310 データシート(PDF) 62 Page - STMicroelectronics

部品番号 STV2310
部品情報  Multistandard TV Digital Video Decoder with Adaptive Comb Filter and RGB/YCrCb Input
PDF  112 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STV2310 データシート(HTML) 62 Page - STMicroelectronics

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Register List
STV2310
62/112
DDECCONT6
Register Description
CRCBOVER_EN
RGB enables the CRCB overload algorithm
This bit enables the RGB CrCb overload mechanism. This mechanism is used to prevent clipping on YCrCb
(when the input RGB signals are too large). The CrCb overload mechanism performs chroma measurement
during the video line to compute the correcting scale factor.
0: CRCB overload algorithm not active
1: CRCB overload algorithm active
FBLANKMODE
[2:0]
Fast Blanking Mode Selection
The Fast Blanking mode is only operational when the STV2310 is not in Analog YCrCb mode. It also
depends on the programmed mode and the FB input value. See register
DDECCONT6.
00x: Normal mixing mode between CVBS and RGB (Default)
(FB active during active line; soft mixing between 0 and 1)
01x: Saturated mode (mixing mode between CVBS and RGB)
(FB active and soft mixing from 0 to MIXSLOPE[7:0])
100: Static Mixer or Alpha Blending Mode 1
(FB inactive) YOUT = alpha x YRGB + (1-alpha) x YCVBS
101: Static Mixer or Alpha Blending Mode 2
(FB inactive) YOUT = alpha x YCVBS + (1- alpha) x YRGB with alpha = MIXSLOPE[7:0]
(Same relationship for Cr and Cb)
110: Forced CVBS (FB inactive) YOUT = YCVBS (idem for Cb, Cr)
111: Forced RGB (FB inactive) YOUT = YRGB (idem for Cb,Cr)
YCRCB_MODE
YCrCb Mode Selection
When the STV2310 is in Analog YCrCb mode, Fast Blanking Mode is disabled.
0: YCrCb signals all either from CVBS or RGB. (Default)
1: YCrCb mode: Y from CVBS signal, Cr and Cb from RGB signal with priority over FB mode.
PHSHFT_DIS
Phase Shift Option Disabled in Output PLL
This bit disables the phase jumps mechanism in the output PLL. Phase jumps are allowed when a phase
shift in the video input is transmitted in the data flow to the output PLL.
0: Phase shifts are enabled. (Default)
1: Phase shifts are disabled.
Address (hex): 06h
Reset Value (bin): 0000 0001
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MIX_SLOPE[7:0]
Bit Name
Function



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