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STV2310 データシート(PDF) 7 Page - STMicroelectronics |
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STV2310 データシート(HTML) 7 Page - STMicroelectronics |
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7 / 112 page  7/112 STV2310 General Description either by an embedded crystal oscillator or an external clock generator (27 MHz).The only exception is the output stage which operates at the line-locked output pixel clock frequency. Figure 2: Architectural Block Diagram Standard Identifier PAL/NTSC/SECAM Analog Input VBI Slicer Soft Mixer Format Converter I²C Interface CVBS1/Y CVBS2/Y C R/Cr G B/Cb FB YCrCb[7:0] HSYNC VSYNC Line-locked & Chroma Demodulator & Output Scaler 27 MHz Field Input SRC Luma Chroma Separator Synchronization and Monitoring Unit Stage Output FIFO Line-locked Output Pixel Clock Video Correction RGB/CrCb System Clock Generation Ouput Pixel Clock SDA SCL CLKSEL CLKXTH PLLLOCK/IRQ 4H/2D Comb Filter Processing CrCb Tint RGB Gain FB Delay Adaptive Luminance Delay |
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