STV2310 datasheet(31/112 Pages) STMICROELECTRONICS

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STV2310

Functional Description

For all output standards, the Vsync output signal changes twice per frame. The Vsync signal (pin

34) can be generated at the output in one of two modes:

“Digital“ Vsync mode: The VSYNC signal always changes at the beginning of the line,

depending on the output standard.

“Analog” Vsync mode: The VSYNC signal changes either at the beginning or the middle of the

line, depending on the analog input signal.

➢ for Output Standard 1: Start of line 4 and middle of line 266

➢ for Output Standard 2: Start of line 1 and middle of line 313

➢ for Output Standard 3: Start of line 1 and middle of line 313 (same as standard 2)

➢ for Output Standard 4: Start of line 4 and middle of line 266

Note that the output standard depends on the input TV standard and the programmable Normal

Pixel or Square Pixel mode.

The VSYNC output mode is selected by the VSYNCTYPE bit in the DDECCONT0 register.

The V bit of the output flow always changes at the beginning of the line (in compliance with standard

ITU-R BT 656).

Non-Interlaced mode: When required, the STV2310 is able to interlace the output, even if the

source is non-interlaced (by default, the output Vsync follows the input Vsync).

4.12.2.3 Hsync Output Pin Mode

The Hsync output pulse can shifted, this is in comparision with the embedded Hsync pulse.

4.12.2.4 FIELD Output Pin Mode

The FIELD output pulse represents the parity of the field and toggles either with the embedded

FIELD pulse, or is synchronous with the Vsync pin, when set in analog interlaced mode. To toggle

in analog interlaced mode, the direct parity mode must be selected.

STV2310 データシート(PDF) 31 Page - STMicroelectronics