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STV2310 データシート(PDF) 76 Page - STMicroelectronics |
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STV2310 データシート(HTML) 76 Page - STMicroelectronics |
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76 / 112 page  Register List STV2310 76/112 DDECCONT23 Register Description DDECCONT24 Register Description DDECCONT25 Register Description HSYNCSHIFT_D EL[1:0] This register allows a programmable delay of HSYNC output signal. This register is only active when o_hsyncshift_en is active (see register DDECCONT22[0]). 00: (no details yet) HSYNCSHIFT_E N Output Synchronisation shift enable 0: No delay (Default) 1: HSYNC is delayed with respect to the digital ouput. Note that this feature has not been decided yet. Address (hex): 23h Reset Value (bin): 1010 1010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Function Bits [7:4] Reserved. Must be set to 1010. Bits [3:0] Reserved. Must be set to 1010. Address (hex): 24h Reset Value (bin): 1000 0111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX_PJ_AMP[3:0] ERR_THRESHOLD[2:0] PJ_EN Bit Name Function Bits [7:4] Reserved. Must be set to 1000. Bits [3:1] Reserved. Must be set to 011. Bit 0 Reserved. Must be set to 1. Address (hex): 25h Reset Value (bin): 1001 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HSYNC_ SAV NOISE_THRESHOLD[2:0] Bit Name Function |
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