STV2310 datasheet(18/112 Pages) STMICROELECTRONICS

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Functional Description

STV2310

18/112

The external HSync pulse can be synchronised to the End of Active Video (EAV) and the Start of

Active Video (SAV) pulses, or initialized according to the usual analog H/V pulse using the

HSYNC_SAV bit in the DDECCONT25 register.

4.3

Input Sample Rate Conversion

4.3.1

General Description

An Input Sample Rate Converter (ISRC) converts the acquisition pixel rate to a clock domain

virtually locked to the color subcarrier. This ISRC is controlled by a subcarrier phased-locked loop

(Chroma PLL). This enables comb filtering and chroma demodulation to be carried out on various

subcarrier frequencies using the same system clock sampling frequency.

The Input SRC uses the data provided by the front-end ADCs to process both the CVBS and C

flows (in the event of separated Y/C inputs, the CVBS flow = Y flow). The same processing is

applied to the CVBS and C data.

When the input video standard has been identified, its subcarrier frequency (fSC) is known and the

Chroma PLL is locked. The Input SRC transforms the input data captured at the 27-MHz system

clock sampling frequency (fS) to the subcarrier clock domain frequency (4 x fSC).

Figure 9: AGC Flowchart

Code

1020

256/244

807 + 8x

772 + 8x

Points/Line

Threshold

108

Threshold

Line

220

Hsync Pulse Bottom Period

Small Amplitude Signal

for Hsync Pulse Bottom Period

Luma Low Signal Detection Threshold

Luma Saturation Threshold

0 to 65

CVBS Saturation Threshold

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