STV2310 datasheet(16/112 Pages) STMICROELECTRONICS

16 / 112 page

Functional Description

STV2310

16/112

Analog R_PR, G and B_PB signals are clamped to the black level during the back porch period.

These signals are digitized by a triple 8-bit A/D converter. It is recommended that an external anti-

aliasing filter be added before each channel input.

The analog insertion (Fast Blanking) signal is sliced and sent to a shaper, controlling the soft

switching between the analog R, G and B signals and the decoded main picture CVBS stream.

All reference voltages required by the A/D Converter are internally generated. Only two pairs of

reference levels, REFP and REFM must be decoupled externally (REFP_CVBS and REFM_CVBS,

REFP_RGB and REFM_RGB ).

4.1.2

Programming

The channel for the desired CVBS signal source is selected by the CVBSMUX bit in the

DDECCONT0 register. The AGC and clamp mechanisms are described in Section 4.2.

4.2

Synchronization and Monitoring Unit

4.2.1

General Description

The STV2310 system clock sampling frequency is provided by a free-running embedded crystal

oscillator or an external clock generator. The nominal value of this sampling frequency is 27 MHz

and is independent of any input TV standard.

Synchronization data (horizontal and vertical sync signals) is extracted from the video signal. After

a low pass stage removing all high frequency information and noise, the video signal is sent to a

synchronization slicer. Then the horizontal and vertical pulses are separated to generate the Hsync

and Vsync pulses. The extracted Hsync pulses are sent to the horizontal PLL (HPLL) in order to

filter the jitter. The HPLL has an adaptive time constant with noise level and other operating

conditions. It provides an easy lock even in difficult conditions and performs the skew extraction.

Using this data, skew correction on the data stream is performed by the output scaler. This PLL can

hold a frequency range of

±8% of the H frequency. A second PLL, associated with the output FIFO,

is used to perform the line-locked clock generation from which the output HSYNC and VSYNC

pulses are obtained by synchronous division.

A vertical sync processor is used to generate the output Vsync pulse, synchronous to the incoming

CVBS signal. This processor is able to automatically detect 50 Hz/60 Hz standards. In the event of

missing pulses, the Vsync processor replaces the missing pulse by inserting a V-pulse at the end of

the 50 Hz or 60 Hz windows.

If an input video signal (CVBS or S-Video) is not detected, the sync processor operates in Free-

running mode.

Figure 8: Anti-Aliasing FIlter for R_PR, G and B_PB Input Signals

B_PB

R_PR

22 nF

R/Cr

B/Cb

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