AD9520-3SLASHPCBZ datasheet(32/84 Pages) AD

32 / 84 page

AD9520-3

Rev. 0 | Page 32 of 84

Mode 2: High Frequency Clock Distribution—CLK or

External VCO > 1600 MHz

The AD9520 power-up default configuration has the PLL

powered off and the routing of the input set so that the CLK/

CLK input is connected to the distribution section through the

VCO divider (divide-by-1/divide-by-2/divide-by-3/ divide-by-4/

divide-by-5/divide-by-6). This is a distribution only mode that

allows for an external input up to 2400 MHz (see

). The

maximum frequency that can be applied to the channel dividers

is 1600 MHz; therefore, higher input frequencies must be divided

down before reaching the channel dividers.

Table 3

When the PLL is enabled, this routing also allows the use of the

PLL with an external VCO or VCXO with a frequency <2400 MHz.

In this configuration, the internal VCO is not used and is powered

off. The external VCO/VCXO feeds directly into the prescaler.

The register settings shown in Table 26 are the default values of

these registers at power-up or after a reset operation.

Table 26. Default Register Settings for Clock Distribution

Mode

Description

0x010[1:0] = 01b

PLL asynchronous power-down (PLL off )

0x1E0[2:0] = 000b

Set VCO divider = 2

0x1E1[0] = 0b

Use the VCO divider

0x1E1[1] = 0b

CLK selected as the source

When using the internal PLL with an external VCO, the PLL

must be turned on.

Table 27. Settings When Using an External VCO

Description

0x010[1:0] = 00b

PLL normal operation (PLL on)

0x010 to 0x01E

PLL settings; select and enable a

reference input; set R, N (P, A, B), PFD

polarity, and ICP according to the intended

loop configuration

0x1E1[1] = 0b

CLK selected as the source

An external VCO requires an external loop filter that must be

connected between CP and the tuning pin of the VCO. This

loop filter determines the loop bandwidth and stability of the

PLL. Make sure to select the proper PFD polarity for the VCO

being used.

Table 28. Setting the PFD Polarity

Description

0x010[7] = 0b

PFD polarity positive (higher control

voltage produces higher frequency)

0x010[7] = 1b

PFD polarity negative (higher control

voltage produces lower frequency)

AD9520-3/PCBZ データシート(PDF) 32 Page - Analog Devices

AD9520-3/PCBZ データシート(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

データシートダウンロード

リンク URL

AD9520-3/PCBZ データシート(PDF) 32 Page - Analog Devices

AD9520-3/PCBZ データシート(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

データシート ダウンロード

リンク URL

データシートダウンロード