AD9520-3SLASHPCBZ datasheet(50/84 Pages) AD

50 / 84 page

AD9520-3

Rev. 0 | Page 50 of 84

Soft Reset via the Serial Port

The serial port control register allows for a soft reset by setting

Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,

the chip enters a soft reset mode and restores the chip either to

the setting stored in EEPROM (the EEPROM pin = 1) or to the

on-chip setting (the EEPROM pin = 0), except for Register 0x000.

These bits are self-clearing. During the internal reset, the outputs

are held static.

Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via

the Serial Port

The serial port control register allows the chip to be reset to

settings in EEPROM when the EEPROM pin = 1 via 0xB02[1].

This bit is self-clearing. This bit does not have any effect when

the EEPROM pin = 0. It takes ~20 ms for the outputs to begin

toggling after the Soft_EEPROM register is cleared.

POWER-DOWN MODES

Chip Power-Down via PD

The AD9520 can be put into a power-down condition by pulling

the PD pin low. Power-down turns off most of the functions and

currents inside the AD9520. The chip remains in this power-down

state until PD is brought back to logic high. When taken out of

power-down mode, the AD9520 returns to the settings

programmed into its registers prior to the power-down, unless

the registers are changed by new programming while the PD

pin is held low.

Powering down the chip shuts down the currents on the chip,

except for the bias current necessary to maintain the LVPECL

outputs in a safe shutdown mode. The LVPECL bias currents are

needed to protect the LVPECL output circuitry from damage that

can be caused by certain termination and load configurations

when tristated. Because this is not a complete power-down, it

can be called sleep mode. The AD9520 contains special circuitry to

prevent runt pulses on the outputs when the chip is entering or

exiting sleep mode.

When the AD9520 is in a PD power-down, the chip is in the

following state:

•

The PLL is off (asynchronous power-down).

•

The VCO is off.

•

The CLK input buffer is off, but the CLK input dc bias

circuit is on.

•

In differential mode, the reference input buffer is off, but

the dc bias circuit is still on.

•

In singled-ended mode, the reference input buffer is off,

and the dc bias circuit is off.

•

All dividers are off.

•

All CMOS outputs are tristated.

•

All LVPECL outputs are in safe off mode.

•

The serial control port is active, and the chip responds to

commands.

PLL Power-Down

The PLL section of the AD9520 can be selectively powered

down. There are two PLL power-down modes set by

In asynchronous power-down mode, the device powers down as

soon as the registers are updated. In synchronous power-down

mode, the PLL power-down is gated by the charge pump to

prevent unwanted frequency jumps. The device goes into power-

down on the occurrence of the next charge pump event after the

registers are updated.

Distribution Power-Down

The distribution section can be powered down by writing

0x230[1] = 1b, which turns off the bias to the distribution

section. If the LVPECL power-down mode is normal operation

(0b), it is possible for a low impedance load on that LVPECL

output to draw significant current during this power-down. If

the LVPECL power-down mode is set to 1b, the LVPECL output

is not protected from reverse bias and can be damaged under

certain termination conditions.

Individual Clock Output Power-Down

Any of the clock distribution outputs can be powered down

into safe power-down mode by individually writing to the

appropriate registers. The register map details the individual

power-down settings for each output. These settings are found

in Register 0x0F0[0] to Register 0x0FD[0].

Individual Clock Channel Power-Down

Any of the clock distribution channels can be powered down

individually by writing to the appropriate registers. Powering

down a clock channel is similar to powering down an individual

driver, but it saves more power because the dividers are also

powered down. Powering down a clock channel also automatically

powers down the drivers connected to it. The register map

details the individual power-down settings for each output

channel. These settings are found in 0x192[2], 0x195[2],

0x198[2], and 0x19B[2].

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