AD9520-3SLASHPCBZ datasheet(48/84 Pages) AD

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AD9520-3

Rev. 0 | Page 48 of 84

The pipeline delay from the SYNC rising edge to the beginning

of the synchronized output clocking is between 14 cycles and

15 cycles of clock at the channel divider input, plus either one

cycle of the VCO divider input (see

), or one cycle of

the channel divider input (see

), depending on whether

the VCO divider is used. Cycles are counted from the rising

edge of the signal. In addition, there is an additional 1.2 ns (typical)

delay from the SYNC signal to the internal synchronization logic,

as well as the propagation delay of the output driver. The driver

propagation delay is approximately 100 ps for the LVPECL

driver and approximately 1.5 ns for the CMOS driver.

Figure 51

Figure 52

Another common way to execute the SYNC function is by

setting and resetting the soft SYNC bit at 0x230[0]. Both setting

and resetting of the soft SYNC bit require an update all registers

(0x232[0] = 1) operation to take effect.

A SYNC operation brings all outputs that have not been excluded

(by the ignore SYNC bit) to a preset condition before allowing

the outputs to begin clocking in synchronicity. The preset condition

takes into account the settings in each of the channel’s start high

bit and its phase offset. These settings govern both the static state

of each output when the SYNC operation is happening and the

state and relative phase of the outputs when they begin clocking

again upon completion of the SYNC operation. Between outputs

and after synchronization, this allows for the setting of phase offsets.

The AD9520 differential LVPECL outputs are four groups of

three, sharing a channel divider per triplet. In the case of CMOS,

each LVPECL differential pair can be configured as two single-

ended CMOS outputs. The synchronization conditions apply to

all of the drivers that belong to that channel divider.

Each channel (a divider and its outputs) can be excluded from

any SYNC operation by setting the no SYNC bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a SYNC operation, and their

outputs are not synchronized with those of the included channels.

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 51. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input

INPUT TO CLK

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 52. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only

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