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AD9520-3/PCBZ データシート(PDF) 75 Page - Analog Devices |
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AD9520-3/PCBZ データシート(HTML) 75 Page - Analog Devices |
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75 / 84 page ![]() AD9520-3 Rev. 0 | Page 75 of 84 Reg. Addr (Hex) Bit(s) Name Description 01F [2] REF2 frequency > threshold (read-only) Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A[6]. [2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. 01F [1] REF1 frequency > threshold (read-only) Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency set by Register 0x01A[6]. [1] = 0; REF1 frequency is less than the threshold frequency. [1] = 1; REF1 frequency is greater than the threshold frequency. 01F [0] Digital lock detect (read-only) Readback register. Digital lock detect. [0] = 0; PLL is not locked. [0] = 1; PLL is locked. Table 54. Output Driver Control Reg. Addr (Hex) Bit(s) Name Description 0F0 [7] OUT0 format Selects the output type for OUT0. [7] = 0; LVPECL (default). [7] = 1; CMOS. 0F0 [6:5] OUT0 CMOS configuration Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1. [6:5] OUT0A OUT0B 00 Tristate Tristate 01 On Tristate 10 Tristate On 11 (default) On On 0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0. [7] [4] [3] Output Type OUT0A OUT 0B 0 (default) X 0 (default) LVPECL Noninverting Inverting 0 X 1 LVPECL Inverting Noninverting 1 0 (default) 0 CMOS Noninverting Noninverting 1 0 1 CMOS Inverting Inverting 1 1 0 CMOS Noninverting Inverting 1 1 1 CMOS Inverting Noninverting 0F0 [2:1] OUT0 LVPECL differential voltage Sets the LVPECL output differential voltage (VOD). [2] [1] VOD (mV) 0 0 400 0 1 600 1 (default) 0 (default) 780 1 1 960 0F0 [0] OUT0 LVPECL power-down LVPECL power-down. [0] = 0; normal operation (default). [0] = 1; safe power-down. 0F1 [7:0] OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. 0F2 [7:0] OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. 0F3 [7:0] OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. 0F4 [7:0] OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. 0F5 [7:0] OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0. |
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