AD9520-3SLASHPCBZ datasheet(47/84 Pages) AD

47 / 84 page

AD9520-3

Rev. 0 | Page 47 of 84

The internal VCO has a duty cycle of 50%. Therefore, when the

VCO is connected directly to the output, the duty cycle is 50%.

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

Phase Offset or Coarse Time Delay

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 39).

These settings determine the number of cycles (successive rising

edges) of the channel divider input frequency by which to offset, or

delay, the rising edge of the output of the divider. This delay is

with respect to a nondelayed output (that is, with a phase offset

of zero). The amount of the delay is set by five bits loaded into

the phase offset (PO) register plus the start high (SH) bit for

each channel divider. When the start high bit is set, the delay is

also affected by the number of low cycles (M) programmed for

the divider.

It is necessary to use the SYNC function to make phase offsets

effective (see the Synchronizing the Outputs—SYNC Function

section).

Table 39. Setting Phase Offset and Division

Divider

Start

High (SH)

Phase

Offset (PO)

Low Cycles

High Cycles

0x191[4]

0x191[3:0]

0x190[7:4]

0x190[3:0]

0x194[4]

0x194[3:0]

0x193[7:4]

0x193[3:0]

0x197[4]

0x197[3:0]

0x196[7:4]

0x196[3:0]

0x19A[4]

0x19A[3:0]

0x199[7:4]

0x199[3:0]

Let

Δt = delay (in seconds).

Δc = delay (in cycles of clock signal at input to DX).

TX = period of the clock signal at the input of the divider, DX (in

seconds).

Φ =

16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]

The channel divide by is set as N = high cycles and M = low

cycles.

Case 1

For Φ ≤ 15,

Δt = Φ × TX

Δc = Δt/TX = Φ

Case 2

For Φ ≥ 16,

Δt = (Φ − 16 + M + 1) × TX

Δc = Δt/TX

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 50 shows the results of setting such a coarse

offset between outputs.

9 10 11 12 13 14 15

DIVIDER 0

DIVIDER 1

DIVIDER 2

CHANNEL

DIVIDER INPUT

SH = 0

PO = 0

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

CHANNEL DIVIDER OUTPUTS

DIV = 4, DUTY = 50%

Figure 50. Effect of Coarse Phase Offset (or Delay)

Synchronizing the Outputs—SYNC Function

The AD9520 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions. These conditions include the

divider ratio and phase offsets for a given channel divider. This

allows the user to specify different divide ratios and phase offsets

for each of the four channel dividers. Releasing the SYNC pin

allows the outputs to continue clocking with the preset conditions

applied.

Synchronization of the outputs is executed in several ways:

• The SYNC pin is forced low and then released (manual sync).

• By setting and then resetting any one of the following three

bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5]

[mirrored]), and the power-down distribution reference bit

(0x230[1]).

• Synchronization of the outputs can be executed as part of the

chip power-up sequence.

• The RESET pin is forced low and then released (chip reset).

• The PD pin is forced low and then released (chip power-down).

• Whenever a VCO calibration is completed, an internal SYNC

signal is automatically asserted at the beginning and released

upon the completion of a VCO calibration.

The most common way to execute the SYNC function is to use

the SYNC pin to perform a manual synchronization of the outputs.

This requires a low-going signal on the SYNC pin, which is held

low and then released when synchronization is desired. The

timing of the SYNC operation is shown in

(using the

VCO divider) and in

(the VCO divider not used).

There is an uncertainty of up to 1 cycle of the clock at the input

to the channel divider due to the asynchronous nature of the

SYNC signal with respect to the clock edges inside the AD9520.

Figure 51

Figure 52

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