AD9520-3SLASHPCBZ datasheet(35/84 Pages) AD

35 / 84 page

AD9520-3

Rev. 0 | Page 35 of 84

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs and

tells the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the internal VCO through the LF pin (or the

tuning pin of an external VCO) to move the VCO frequency up

or down. The CP can be set (0x010[3:2]) for high impedance

(allows holdover operation), for normal operation (attempts to

lock the PLL loop), for pump up, or for pump down (test modes).

The CP current is programmable in eight steps from (nominally)

600 μA to 4.8 mA. The exact value of the CP current LSB is set

by the CPRSET resistor, which is nominally 5.1 kΩ.

On-Chip VCO

The AD9520 includes an on-chip VCO covering the frequency

range shown in Table 2. Achieving low VCO phase noise was a

priority in the design of the VCO.

To tune over the wide range of frequencies covered by this

VCO, ranges are used. This is largely transparent to the user

but is the reason that the VCO must be calibrated when the PLL

loop is first set up. The calibration procedure ensures that the

VCO is operating within the correct band range for the desired

VCO frequency. See the VCO Calibration section for additional

information.

The on-chip VCO is powered by an on-chip, low dropout (LDO),

linear voltage regulator. The LDO provides some isolation of

the VCO from variations in the power supply voltage level.

The BYPASS pin should be connected to ground by a 220 nF

capacitor to ensure stability. This LDO employs the same

technology used in the anyCAP® line of regulators from Analog

Devices, Inc., making it insensitive to the type of capacitor used.

Driving an external load from the BYPASS pin is not supported.

PLL External Loop Filter

When using the internal VCO, the external loop filter should be

referenced to the BYPASS pin for optimal noise and spurious

performance. An example of an external loop filter for the PLL

is shown in Figure 41. A loop filter must be calculated for each

desired PLL configuration. The values of the components depend

upon the VCO frequency, the KVCO, the PFD frequency, the CP

current, the desired loop bandwidth, and the desired phase margin.

The loop filter affects the phase noise, the loop settling time,

and the loop stability. A knowledge of PLL theory is necessary

for understanding loop filter design. Tools available, such as the

ADIsimCLK, can help with the calculation of a loop filter

according to the application requirements.

VCO

CHARGE

PUMP

BYPASS

CBP = 220nF

AD9520

Figure 41. Example of External Loop Filter for PLL

PLL Reference Inputs

The AD9520 features a flexible PLL reference input circuit that

allows a fully differential input, two separate single-ended inputs,

or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip

maintaining amplifier. An optional reference clock doubler

can be used to double the PLL reference frequency. The input

frequency range for the reference inputs is specified in Table 2.

Both the differential and the single-ended inputs are self-biased,

allowing for easy ac coupling of input signals.

Either a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential input and the single-ended inputs share two pins,

REFIN (REF1) and REFIN (REF2). The desired reference input

type is selected and controlled by 0x01C (see

and

Table 49

Table 53

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly to prevent chattering of

the input buffer when the reference is slow or missing. The

specification for this voltage level can be found in Table 2.

The input hysteresis increases the voltage swing required of

the driver to overcome the offset.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave.

To avoid input buffer chatter when a single-ended, ac-coupled

input signal stops toggling, the user can set 0x018[7] to 1. This

shifts the dc offset bias point down 140 mV. To increase isolation

and reduce power, each single-ended input can be independently

powered down.

The differential reference input receiver is powered down when

the differential reference input is not selected or when the PLL

is powered down. The single-ended buffers power down when

the PLL is powered down or when their respective individual

power-down registers are set. When the differential mode is

selected, the single-ended inputs are powered down.

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