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AD9520-3/PCBZ データシート(PDF) 78 Page - Analog Devices |
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AD9520-3/PCBZ データシート(HTML) 78 Page - Analog Devices |
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78 / 84 page  AD9520-3 Rev. 0 | Page 78 of 84 Reg. Addr (Hex) Bit(s) Name Description 197 [6] Divider 2 ignore SYNC No SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 197 [5] Divider 2 force high Forces divider output to high. This requires that no SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 197 [4] Divider 2 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 197 [3:0] Divider 2 phase offset Phase offset(default: 0x0). 198 [2] Channel 2 power-down Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe power- down mode by setting this bit.) 198 [1] Channel 2 direct-to-output Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK. [1] = 0; OUT6, OUT7, and OUT8 are connected to Divider 2 (default). [1] = 1: If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8. If 0x1E1[1:0] = 01b, there is no effect. 198 [0] Disable Divider 2 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 199 [7:4] Divider 3 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0). 199 [3:0] Divider 3 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0). 19A [7] Divider 3 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 19A [6] Divider 3 ignore SYNC No SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 19A [5] Divider 3 force high Forces divider output to high. This requires that no SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 19A [4] Divider 3 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 19A [3:0] Divider 3 phase offset Phase offset (default: 0x0). 19B [2] Channel 3 power-down Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into safe power-down mode by setting this bit.) |
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