AD9520-3SLASHPCBZ datasheet(43/84 Pages) AD

43 / 84 page

AD9520-3

Rev. 0 | Page 43 of 84

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLK/CLK

DIVIDER

DELAY

DIVIDER

DELAY

PFD

LOOP

FILTER

MUX1

REG 0x01E[1] = 1

REFIN/

REFIN

REG 0x01E[0]

ZERO DELAY

INTERNAL FEEDBACK PATH

EXTERNAL FEEDBACK PATH

ZERO DELAY FEEDBACK CLOCK

CHANNEL DIVIDER 0

CHANNEL DIVIDER 1

CHANNEL DIVIDER 2

CHANNEL DIVIDER 3

OUT0 TO OUT2

OUT3 TO OUT5

OUT6 TO OUT8

OUT9 TO OUT11

AD9520

Figure 48. Zero Delay Function

ZERO DELAY OPERATION

Zero delay operation aligns the phase of the output clocks with

the phase of the external PLL reference input. There are two

zero delay modes on the AD9520: internal and external.

Internal Zero Delay Mode

The internal zero delay function of the AD9520 is achieved by

feeding the output of Channel Divider 0 back to the PLL N

divider. In Figure 48, the change in signal routing for internal

zero delay mode is shown in blue.

Internal zero delay mode is selected by setting Register

0x01E[2:1] = 01b. In the default internal zero delay mode,

the output of Channel Divider 0 is routed back to the PLL (N

divider) through Mux3 and Mux1 (feedback path shown in blue

in Figure 48). The PLL synchronizes the phase/edge of the output

of Channel Divider 0 with the phase/edge of the reference input.

The user can also specify Channel Divider 1, Channel Divider 2,

or Channel Divider 3 for zero delay feedback by changing the

value in Register 0x01E[4:3].

Because the channel dividers are synchronized to each other,

the outputs of the channel divider are synchronous with the

reference input. Both the R delay and the N delay inside the

PLL can be programmed to compensate for the propagation

delay from the output drivers and PLL components to minimize

the phase offset between the clock output and the reference

input to achieve zero delay.

External Zero Delay Mode

The external zero delay function of the AD9520 is achieved by

feeding one clock output back to the CLK input and ultimately

back to the PLL N divider. In Figure 48, the change in signal

routing for external zero delay mode is shown in red.

External zero delay mode is selected by setting 0x01E[2:1] = 11.

In external zero delay mode, one of the twelve output clocks

(OUT0 to OUT11) can be routed back to the PLL (N divider)

through the CLK/CLK pins and through Mux3 and Mux1. This

feedback path is shown in red in

Figure 48

The PLL synchronizes the phase/edge of the feedback output clock

with the phase/edge of the reference input. Because the channel

dividers are synchronized to each other, the clock outputs are

synchronous with the reference input. Both the R delay and the

N delay inside the PLL can be programmed to compensate for

the propagation delay from the PLL components to minimize the

phase offset between the feedback clock and the reference input.

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