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KAI-08052 データシート(PDF) 6 Page - ON Semiconductor |
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KAI-08052 データシート(HTML) 6 Page - ON Semiconductor |
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6 / 33 page  KAI−08052 www.onsemi.com 6 Table 3. PIN DESCRIPTION Pin Name Description 1 V3B Vertical CCD Clock, Phase 3, Bottom 3 V1B Vertical CCD Clock, Phase 1, Bottom 4 V4B Vertical CCD Clock, Phase 4, Bottom 5 VDDa Output Amplifier Supply, Quadrant a 6 V2B Vertical CCD Clock, Phase 2, Bottom 7 GND Ground 8 VOUTa Video Output, Quadrant a 9 Ra Reset Gate, Quadrant a 10 RDa Reset Drain, Quadrant a 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 17 N/C No Connect 18 SUB Substrate 19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 23 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 24 OGb Output Gate, Quadrant b 25 Rb Reset Gate, Quadrant b 26 RDb Reset Drain, Quadrant b 27 GND Ground 28 VOUTb Video Output, Quadrant b 29 VDDb Output Amplifier Supply, Quadrant b 30 V2B Vertical CCD Clock, Phase 2, Bottom 31 V1B Vertical CCD Clock, Phase 1, Bottom 32 V4B Vertical CCD Clock, Phase 4, Bottom 33 V3B Vertical CCD Clock, Phase 3, Bottom 34 ESD ESD Protection Disable Pin Name Description 68 ESD ESD Protection Disable 67 V3T Vertical CCD Clock, Phase 3, Top 66 V4T Vertical CCD Clock, Phase 4, Top 65 V1T Vertical CCD Clock, Phase 1, Top 64 V2T Vertical CCD Clock, Phase 2, Top 63 VDDc Output Amplifier Supply, Quadrant c 62 VOUTc Video Output, Quadrant c 61 GND Ground 60 RDc Reset Drain, Quadrant c 59 Rc Reset Gate, Quadrant c 58 OGc Output Gate, Quadrant c 57 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 56 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 55 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 54 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 53 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 52 SUB Substrate 51 N/C No Connect 50 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 49 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 48 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 47 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 46 OGd Output Gate, Quadrant d 45 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d 44 RDd Reset Drain, Quadrant d 43 Rd Reset Gate, Quadrant d 42 VOUTd Video Output, Quadrant d 41 GND Ground 40 V2T Vertical CCD Clock, Phase 2, Top 39 VDDd Output Amplifier Supply, Quadrant d 38 V4T Vertical CCD Clock, Phase 4, Top 37 V1T Vertical CCD Clock, Phase 1, Top 36 DevID Device Identification 35 V3T Vertical CCD Clock, Phase 3, Top 1. Liked named pins are internally connected and should have a common drive signal. 2. N/C pins (17, 51) should be left floating. |
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