KAI−08052

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18

The VCCD clock waveform must not have a negative

overshoot more than 0.4 V below the ESD voltage.

Figure 16.

All VCCD Clocks absolute

maximum overshoot of 0.4 V

0.0 V

ESD

ESD − 0.4 V

Example of external diode protection for SUB, VDD and

ESD.

a denotes a, b, c or d

Figure 17.

GND

SUB

VDDa

ESD

Table 15. DC BIAS OPERATING CONDITIONS

Description

Pins

Symbol

Minimum

Nominal

Maximum

Units

Maximum DC

Current

Notes

Reset Drain

RDa

RD

11.8

12.0

12.2

V

10 mA

1

Output Gate

OGa

OG

−2.2

−2.0

−1.8

V

10 mA

1

Output Amplifier Supply

VDDa

VDD

14.5

15.0

15.5

V

11.0 mA

1, 2

Ground

GND

GND

0.0

0.0

0.0

V

−1.0 mA

Substrate

SUB

VSUB

5.0

VAB

VDD

V

50 mA

3, 8

ESD Protection Disable

ESD

ESD

−9.2

−9.0

Vx_L

V

50 mA

6, 7, 9

Output Bias Current

VOUTa

Iout

−3.0

−7.0

−10.0

mA

1, 4, 5

1. a denotes a, b, c or d

2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 18.

3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such

that the photodiode charge capacity is the nominal PNe (see Specifications).

4. An output load sink must be applied to each VOUT pin to activate each output amplifier.

5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.

6. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section.

7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V

8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D)

9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.