KAI−08052

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23

Timing Diagrams

The timing sequence for the clocked device pins may be

represented as one of seven patterns (P1−P7) as shown in the

table below. The patterns are defined in Figure 21 and

Figure 22. Contact ON Semiconductor Application

Engineering for other readout modes.

Table 19.

Device Pin

Quad Readout

Dual Readout

VOUTa, VOUTb

Dual Readout

VOUTa, VOUTc

Single Readout

VOUTa

V1T

P1T

P1B

P1T

P1B

V2T

P2T

P4B

P2T

P4B

V3T

P3T

P3B

P3T

P3B

V4T

P4T

P2B

P4T

P2B

V1B

P1B

V2B

P2B

V3B

P3B

V4B

P4B

H1Sa

P5

H1Ba

H2Sa2

P6

H2Ba

Ra

P7

H1Sb

P5

P5

H1Bb

P6

P6

P6

H2Bb

P5

Rb

P7

H1Sc

P5

P5

H1Bc

P6

P6

H2Bc

Rc

P7

P7

H1Sd

P5

P5

H1Bd

P6

P6

P6

H2Bd

P5

Rd

P7

# Lines/Frame (Minimum)

1260

2520

1260

2520

# Pixels/Line (Minimum)

1693

3386

1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should

be a multiple of the frequency used on the a and b register.

2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver.

3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the

unused c/d register into the image area.