KAI−08052

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20

AC Operating Conditions

Table 16. CLOCK LEVELS

Description

Symbol

Level

Minimum

Nominal

Maximum

Units

Vertical CCD Clock,

Phase 1

V1B, V1T

V1_L

Low

−8.2

−8.0

−7.8

V

V1_M

Mid

−0.2

0.0

0.2

V1_H

High

11.5

12.0

12.5

Vertical CCD Clock,

Phase 2

V2B, V2T

V2_L

Low

−8.2

−8.0

−7.8

V

V2_H

High

−0.2

0.0

0.2

Vertical CCD Clock,

Phase 3

V3B, V3T

V3_L

Low

−8.2

−8.0

−7.8

V

V3_H

High

−0.2

0.0

0.2

Vertical CCD Clock,

Phase 4

V4B, V4T

V4_L

Low

−8.2

−8.0

−7.8

V

V4_H

High

−0.2

0.0

0.2

Horizontal CCD Clock,

Phase 1 Storage

H1Sa

H1S_L

Low

−4.0

−3.8

V

H1S_A

Amplitude

3.8

4.0

Horizontal CCD Clock,

Phase 1 Barrier

H1Ba

H1B_L

Low

−4.0

−3.8

V

H1B_A

Amplitude

3.8

4.0

Horizontal CCD Clock,

Phase 2 Storage

H2Sa

H2S_L

Low

−4.0

−3.8

V

H2S_A

Amplitude

3.8

4.0

Horizontal CCD Clock,

Phase 2 Barrier

H2Ba

H2B_L

Low

−4.0

−3.8

V

H2B_A

Amplitude

3.8

4.0

Horizontal CCD Clock,

H2SLa

H2SL_L

Low

−5.2

−5.0

−4.8

V

H2SL_A

Amplitude

4.8

5.0

5.2

Reset Gate

Ra

Low

−3.5

−2.0

−1.5

V

R_H

High

2.5

3.0

4.0

SUB

VES

High

29.0

30.0

40.0

V

1. a denotes a, b, c or d

2. Capacitance is total for all like named pins

3. Use separate clock driver for improved speed performance.

4. Reset low should be set to –3 V for signal levels greater than 40,000 electrons.

5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D)

6. Capacitance values are estimated

7. If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude)

to create a –5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to –5.0 V and the high level should be

a set to 0.0 V.

The figure below shows the DC bias (VSUB) and AC

clock (VES) applied to the SUB pin. Both the DC bias and

AC clock are referenced to ground.

Figure 19.

VSUB

VES

GND

GND